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0588ed70 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
0588ed70 | 3 | ## |
d94ff143 | 4 | ## Copyright (C) 2010-2013 Uwe Hermann <uwe@hermann-uwe.de> |
0588ed70 UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
0588ed70 | 21 | # TODO: Look into arbitration, collision detection, clock synchronisation, etc. |
9e95e4d8 | 22 | # TODO: Implement support for 10bit slave addresses. |
0588ed70 UH |
23 | # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0). |
24 | # TODO: Implement support for detecting various bus errors. | |
23fb2e12 | 25 | |
677d597b | 26 | import sigrokdecode as srd |
b2c19614 | 27 | |
f1428c4c | 28 | ''' |
c515eed7 | 29 | OUTPUT_PYTHON format: |
f1428c4c | 30 | |
ab4aa33c | 31 | I²C packet: |
f1428c4c UH |
32 | [<cmd>, <data>] |
33 | ||
34 | <cmd> is one of: | |
35 | - 'START' (START condition) | |
36 | - 'START REPEAT' (Repeated START condition) | |
37 | - 'ADDRESS READ' (Slave address, read) | |
38 | - 'ADDRESS WRITE' (Slave address, write) | |
39 | - 'DATA READ' (Data, read) | |
40 | - 'DATA WRITE' (Data, write) | |
41 | - 'STOP' (STOP condition) | |
42 | - 'ACK' (ACK bit) | |
43 | - 'NACK' (NACK bit) | |
44 | ||
45 | <data> is the data or address byte associated with the 'ADDRESS*' and 'DATA*' | |
46 | command. Slave addresses do not include bit 0 (the READ/WRITE indication bit). | |
47 | For example, a slave address field could be 0x51 (instead of 0xa2). | |
48 | For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' <data> is None. | |
49 | ''' | |
50 | ||
d94ff143 | 51 | # CMD: [annotation-type-index, long annotation, short annotation] |
1541976f | 52 | proto = { |
d94ff143 UH |
53 | 'START': [0, 'Start', 'S'], |
54 | 'START REPEAT': [1, 'Start repeat', 'Sr'], | |
55 | 'STOP': [2, 'Stop', 'P'], | |
56 | 'ACK': [3, 'ACK', 'A'], | |
57 | 'NACK': [4, 'NACK', 'N'], | |
58 | 'ADDRESS READ': [5, 'Address read', 'AR'], | |
59 | 'ADDRESS WRITE': [6, 'Address write', 'AW'], | |
60 | 'DATA READ': [7, 'Data read', 'DR'], | |
61 | 'DATA WRITE': [8, 'Data write', 'DW'], | |
15969949 | 62 | } |
e5080882 | 63 | |
677d597b | 64 | class Decoder(srd.Decoder): |
a2c2afd9 | 65 | api_version = 1 |
67e847fd | 66 | id = 'i2c' |
ab4aa33c | 67 | name = 'I²C' |
9a12a6e7 | 68 | longname = 'Inter-Integrated Circuit' |
a465436e | 69 | desc = 'Two-wire, multi-master, serial bus.' |
f39d2404 UH |
70 | license = 'gplv2+' |
71 | inputs = ['logic'] | |
72 | outputs = ['i2c'] | |
bc5f5a43 BV |
73 | probes = [ |
74 | {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'}, | |
75 | {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'}, | |
76 | ] | |
b77614bc | 77 | optional_probes = [] |
f39d2404 | 78 | options = { |
d94ff143 | 79 | 'address_format': ['Displayed slave address format', 'shifted'], |
ad2dc0de | 80 | } |
e97b6ef5 | 81 | annotations = [ |
fbd226c3 BV |
82 | ['start', 'Start condition'], |
83 | ['repeat-start', 'Repeat start condition'], | |
84 | ['stop', 'Stop condition'], | |
85 | ['ack', 'ACK'], | |
86 | ['nack', 'NACK'], | |
87 | ['address-read', 'Address read'], | |
88 | ['address-write', 'Address write'], | |
89 | ['data-read', 'Data read'], | |
90 | ['data-write', 'Data write'], | |
91 | ['warnings', 'Human-readable warnings'], | |
15969949 | 92 | ] |
a929afa6 | 93 | binary = ( |
5cb2cb02 BV |
94 | ('address-read', 'Address read'), |
95 | ('address-write', 'Address write'), | |
96 | ('data-read', 'Data read'), | |
97 | ('data-write', 'Data write'), | |
a929afa6 | 98 | ) |
0588ed70 | 99 | |
3643fc3f | 100 | def __init__(self, **kwargs): |
8d2a9636 | 101 | self.samplerate = None |
c4975078 BV |
102 | self.startsample = -1 |
103 | self.samplenum = None | |
f39d2404 UH |
104 | self.bitcount = 0 |
105 | self.databyte = 0 | |
106 | self.wr = -1 | |
5dd9af5b | 107 | self.is_repeat_start = 0 |
2b716038 | 108 | self.state = 'FIND START' |
95097f31 UH |
109 | self.oldscl = 1 |
110 | self.oldsda = 1 | |
d94ff143 | 111 | self.oldpins = [1, 1] |
8d2a9636 BV |
112 | self.pdu_start = None |
113 | self.pdu_bits = 0 | |
114 | ||
115 | def metadata(self, key, value): | |
116 | if key == srd.SRD_CONF_SAMPLERATE: | |
117 | self.samplerate = value | |
f39d2404 | 118 | |
8915b346 | 119 | def start(self): |
c515eed7 | 120 | self.out_python = self.register(srd.OUTPUT_PYTHON) |
8d2a9636 | 121 | self.out_ann = self.register(srd.OUTPUT_ANN) |
be6733ca | 122 | self.out_binary = self.register(srd.OUTPUT_BINARY) |
8d2a9636 BV |
123 | self.out_bitrate = self.register(srd.OUTPUT_META, |
124 | meta=(int, 'Bitrate', 'Bitrate from Start bit to Stop bit')) | |
3643fc3f | 125 | |
d94ff143 UH |
126 | def putx(self, data): |
127 | self.put(self.startsample, self.samplenum, self.out_ann, data) | |
128 | ||
129 | def putp(self, data): | |
c515eed7 | 130 | self.put(self.startsample, self.samplenum, self.out_python, data) |
d94ff143 | 131 | |
a929afa6 BV |
132 | def putb(self, data): |
133 | self.put(self.startsample, self.samplenum, self.out_binary, data) | |
134 | ||
7b86f0bc | 135 | def is_start_condition(self, scl, sda): |
eb7082c9 | 136 | # START condition (S): SDA = falling, SCL = high |
7b86f0bc UH |
137 | if (self.oldsda == 1 and sda == 0) and scl == 1: |
138 | return True | |
139 | return False | |
140 | ||
141 | def is_data_bit(self, scl, sda): | |
eb7082c9 | 142 | # Data sampling of receiver: SCL = rising |
7b86f0bc UH |
143 | if self.oldscl == 0 and scl == 1: |
144 | return True | |
145 | return False | |
146 | ||
147 | def is_stop_condition(self, scl, sda): | |
eb7082c9 | 148 | # STOP condition (P): SDA = rising, SCL = high |
7b86f0bc UH |
149 | if (self.oldsda == 0 and sda == 1) and scl == 1: |
150 | return True | |
151 | return False | |
152 | ||
e5080882 | 153 | def found_start(self, scl, sda): |
c4975078 | 154 | self.startsample = self.samplenum |
8d2a9636 BV |
155 | self.pdu_start = self.samplenum |
156 | self.pdu_bits = 0 | |
c4975078 | 157 | cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START' |
d94ff143 UH |
158 | self.putp([cmd, None]) |
159 | self.putx([proto[cmd][0], proto[cmd][1:]]) | |
2b716038 | 160 | self.state = 'FIND ADDRESS' |
7b86f0bc | 161 | self.bitcount = self.databyte = 0 |
5dd9af5b | 162 | self.is_repeat_start = 1 |
7b86f0bc | 163 | self.wr = -1 |
7b86f0bc | 164 | |
c4975078 | 165 | # Gather 8 bits of data plus the ACK/NACK bit. |
e5080882 | 166 | def found_address_or_data(self, scl, sda): |
7b86f0bc UH |
167 | # Address and data are transmitted MSB-first. |
168 | self.databyte <<= 1 | |
169 | self.databyte |= sda | |
170 | ||
c4975078 BV |
171 | if self.bitcount == 0: |
172 | self.startsample = self.samplenum | |
173 | ||
7b86f0bc | 174 | # Return if we haven't collected all 8 + 1 bits, yet. |
c4975078 | 175 | self.bitcount += 1 |
1b75abfd | 176 | if self.bitcount != 8: |
eb7082c9 | 177 | return |
7b86f0bc | 178 | |
1b75abfd BV |
179 | # We triggered on the ACK/NACK bit, but won't report that until later. |
180 | self.startsample -= 1 | |
181 | ||
d94ff143 | 182 | d = self.databyte |
2b716038 | 183 | if self.state == 'FIND ADDRESS': |
7b86f0bc | 184 | # The READ/WRITE bit is only in address bytes, not data bytes. |
bf1c3f4d | 185 | self.wr = 0 if (self.databyte & 1) else 1 |
d94ff143 UH |
186 | if self.options['address_format'] == 'shifted': |
187 | d = d >> 1 | |
15969949 | 188 | |
a929afa6 | 189 | bin_class = -1 |
2b716038 | 190 | if self.state == 'FIND ADDRESS' and self.wr == 1: |
a2d2aff2 | 191 | cmd = 'ADDRESS WRITE' |
a929afa6 | 192 | bin_class = 1 |
2b716038 | 193 | elif self.state == 'FIND ADDRESS' and self.wr == 0: |
a2d2aff2 | 194 | cmd = 'ADDRESS READ' |
a929afa6 | 195 | bin_class = 0 |
2b716038 | 196 | elif self.state == 'FIND DATA' and self.wr == 1: |
a2d2aff2 | 197 | cmd = 'DATA WRITE' |
a929afa6 | 198 | bin_class = 3 |
2b716038 | 199 | elif self.state == 'FIND DATA' and self.wr == 0: |
a2d2aff2 | 200 | cmd = 'DATA READ' |
a929afa6 | 201 | bin_class = 2 |
eb7082c9 | 202 | |
d94ff143 UH |
203 | self.putp([cmd, d]) |
204 | self.putx([proto[cmd][0], ['%s: %02X' % (proto[cmd][1], d), | |
205 | '%s: %02X' % (proto[cmd][2], d), '%02X' % d]]) | |
a929afa6 | 206 | self.putb((bin_class, bytes([d]))) |
7b86f0bc | 207 | |
1b75abfd | 208 | # Done with this packet. |
7b86f0bc | 209 | self.startsample = -1 |
1b75abfd | 210 | self.bitcount = self.databyte = 0 |
2b716038 | 211 | self.state = 'FIND ACK' |
7b86f0bc | 212 | |
1b75abfd BV |
213 | def get_ack(self, scl, sda): |
214 | self.startsample = self.samplenum | |
d94ff143 UH |
215 | cmd = 'NACK' if (sda == 1) else 'ACK' |
216 | self.putp([cmd, None]) | |
217 | self.putx([proto[cmd][0], proto[cmd][1:]]) | |
1b75abfd BV |
218 | # There could be multiple data bytes in a row, so either find |
219 | # another data byte or a STOP condition next. | |
2b716038 | 220 | self.state = 'FIND DATA' |
7b86f0bc | 221 | |
e5080882 | 222 | def found_stop(self, scl, sda): |
8d2a9636 BV |
223 | # Meta bitrate |
224 | elapsed = 1 / float(self.samplerate) * (self.samplenum - self.pdu_start + 1) | |
225 | bitrate = int(1 / elapsed * self.pdu_bits) | |
226 | self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate) | |
227 | ||
c4975078 | 228 | self.startsample = self.samplenum |
d94ff143 UH |
229 | cmd = 'STOP' |
230 | self.putp([cmd, None]) | |
231 | self.putx([proto[cmd][0], proto[cmd][1:]]) | |
2b716038 | 232 | self.state = 'FIND START' |
5dd9af5b | 233 | self.is_repeat_start = 0 |
7b86f0bc UH |
234 | self.wr = -1 |
235 | ||
2b9837d9 | 236 | def decode(self, ss, es, data): |
8d2a9636 BV |
237 | if self.samplerate is None: |
238 | raise Exception("Cannot decode without samplerate.") | |
2fcd7c22 UH |
239 | for (self.samplenum, pins) in data: |
240 | ||
241 | # Ignore identical samples early on (for performance reasons). | |
242 | if self.oldpins == pins: | |
243 | continue | |
244 | self.oldpins, (scl, sda) = pins, pins | |
f39d2404 | 245 | |
8d2a9636 BV |
246 | self.pdu_bits += 1 |
247 | ||
f39d2404 UH |
248 | # TODO: Wait until the bus is idle (SDA = SCL = 1) first? |
249 | ||
7b86f0bc | 250 | # State machine. |
2b716038 | 251 | if self.state == 'FIND START': |
7b86f0bc | 252 | if self.is_start_condition(scl, sda): |
e5080882 | 253 | self.found_start(scl, sda) |
2b716038 | 254 | elif self.state == 'FIND ADDRESS': |
7b86f0bc | 255 | if self.is_data_bit(scl, sda): |
e5080882 | 256 | self.found_address_or_data(scl, sda) |
2b716038 | 257 | elif self.state == 'FIND DATA': |
7b86f0bc | 258 | if self.is_data_bit(scl, sda): |
e5080882 | 259 | self.found_address_or_data(scl, sda) |
7b86f0bc | 260 | elif self.is_start_condition(scl, sda): |
e5080882 | 261 | self.found_start(scl, sda) |
7b86f0bc | 262 | elif self.is_stop_condition(scl, sda): |
e5080882 | 263 | self.found_stop(scl, sda) |
2b716038 | 264 | elif self.state == 'FIND ACK': |
1b75abfd BV |
265 | if self.is_data_bit(scl, sda): |
266 | self.get_ack(scl, sda) | |
7b86f0bc | 267 | else: |
0eeeb544 | 268 | raise Exception('Invalid state: %s' % self.state) |
f39d2404 UH |
269 | |
270 | # Save current SDA/SCL values for the next round. | |
271 | self.oldscl = scl | |
272 | self.oldsda = sda | |
273 |