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0588ed70 UH |
1 | ## |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
7b86f0bc | 4 | ## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de> |
0588ed70 UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
0588ed70 | 21 | # I2C protocol decoder |
0588ed70 UH |
22 | |
23 | # TODO: Look into arbitration, collision detection, clock synchronisation, etc. | |
24 | # TODO: Handle clock stretching. | |
25 | # TODO: Handle combined messages / repeated START. | |
26 | # TODO: Implement support for 7bit and 10bit slave addresses. | |
27 | # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0). | |
28 | # TODO: Implement support for detecting various bus errors. | |
23fb2e12 UH |
29 | # TODO: I2C address of slaves. |
30 | # TODO: Handle multiple different I2C devices on same bus | |
31 | # -> we need to decode multiple protocols at the same time. | |
23fb2e12 | 32 | |
677d597b | 33 | import sigrokdecode as srd |
b2c19614 | 34 | |
eb7082c9 | 35 | # Annotation feed formats |
e4f82268 | 36 | ANN_SHIFTED = 0 |
7ce7775c | 37 | ANN_SHIFTED_SHORT = 1 |
e4f82268 | 38 | ANN_RAW = 2 |
7ce7775c | 39 | |
eb7082c9 | 40 | # Values are verbose and short annotation, respectively. |
1541976f | 41 | proto = { |
eb7082c9 | 42 | 'START': ['START', 'S'], |
a2d2aff2 | 43 | 'START REPEAT': ['START REPEAT', 'Sr'], |
eb7082c9 UH |
44 | 'STOP': ['STOP', 'P'], |
45 | 'ACK': ['ACK', 'A'], | |
46 | 'NACK': ['NACK', 'N'], | |
a2d2aff2 UH |
47 | 'ADDRESS READ': ['ADDRESS READ', 'AR'], |
48 | 'ADDRESS WRITE': ['ADDRESS WRITE', 'AW'], | |
49 | 'DATA READ': ['DATA READ', 'DR'], | |
50 | 'DATA WRITE': ['DATA WRITE', 'DW'], | |
15969949 | 51 | } |
e5080882 | 52 | |
677d597b | 53 | class Decoder(srd.Decoder): |
a2c2afd9 | 54 | api_version = 1 |
67e847fd | 55 | id = 'i2c' |
f39d2404 | 56 | name = 'I2C' |
9a12a6e7 | 57 | longname = 'Inter-Integrated Circuit' |
f39d2404 | 58 | desc = 'I2C is a two-wire, multi-master, serial bus.' |
f39d2404 UH |
59 | license = 'gplv2+' |
60 | inputs = ['logic'] | |
61 | outputs = ['i2c'] | |
bc5f5a43 BV |
62 | probes = [ |
63 | {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'}, | |
64 | {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'}, | |
65 | ] | |
b77614bc | 66 | optional_probes = [] |
f39d2404 | 67 | options = { |
ea90233e | 68 | 'addressing': ['Slave addressing (in bits)', 7], # 7 or 10 |
ad2dc0de | 69 | } |
e97b6ef5 | 70 | annotations = [ |
15969949 | 71 | # ANN_SHIFTED |
eb7082c9 UH |
72 | ['7-bit shifted hex', |
73 | 'Read/write bit shifted out from the 8-bit I2C slave address'], | |
15969949 | 74 | # ANN_SHIFTED_SHORT |
eb7082c9 UH |
75 | ['7-bit shifted hex (short)', |
76 | 'Read/write bit shifted out from the 8-bit I2C slave address'], | |
15969949 | 77 | # ANN_RAW |
eb7082c9 | 78 | ['Raw hex', 'Unaltered raw data'], |
15969949 | 79 | ] |
0588ed70 | 80 | |
3643fc3f | 81 | def __init__(self, **kwargs): |
c4975078 BV |
82 | self.startsample = -1 |
83 | self.samplenum = None | |
f39d2404 UH |
84 | self.bitcount = 0 |
85 | self.databyte = 0 | |
86 | self.wr = -1 | |
5dd9af5b | 87 | self.is_repeat_start = 0 |
2b716038 | 88 | self.state = 'FIND START' |
f39d2404 UH |
89 | self.oldscl = None |
90 | self.oldsda = None | |
91 | ||
3643fc3f | 92 | def start(self, metadata): |
56202222 UH |
93 | self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c') |
94 | self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c') | |
3643fc3f | 95 | |
decde15e UH |
96 | def report(self): |
97 | pass | |
98 | ||
7b86f0bc | 99 | def is_start_condition(self, scl, sda): |
eb7082c9 | 100 | # START condition (S): SDA = falling, SCL = high |
7b86f0bc UH |
101 | if (self.oldsda == 1 and sda == 0) and scl == 1: |
102 | return True | |
103 | return False | |
104 | ||
105 | def is_data_bit(self, scl, sda): | |
eb7082c9 | 106 | # Data sampling of receiver: SCL = rising |
7b86f0bc UH |
107 | if self.oldscl == 0 and scl == 1: |
108 | return True | |
109 | return False | |
110 | ||
111 | def is_stop_condition(self, scl, sda): | |
eb7082c9 | 112 | # STOP condition (P): SDA = rising, SCL = high |
7b86f0bc UH |
113 | if (self.oldsda == 0 and sda == 1) and scl == 1: |
114 | return True | |
115 | return False | |
116 | ||
e5080882 | 117 | def found_start(self, scl, sda): |
c4975078 | 118 | self.startsample = self.samplenum |
eb7082c9 | 119 | |
c4975078 | 120 | cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START' |
1b75abfd | 121 | self.put(self.out_proto, [cmd, None]) |
1541976f UH |
122 | self.put(self.out_ann, [ANN_SHIFTED, [proto[cmd][0]]]) |
123 | self.put(self.out_ann, [ANN_SHIFTED_SHORT, [proto[cmd][1]]]) | |
e5080882 | 124 | |
2b716038 | 125 | self.state = 'FIND ADDRESS' |
7b86f0bc | 126 | self.bitcount = self.databyte = 0 |
5dd9af5b | 127 | self.is_repeat_start = 1 |
7b86f0bc | 128 | self.wr = -1 |
7b86f0bc | 129 | |
c4975078 | 130 | # Gather 8 bits of data plus the ACK/NACK bit. |
e5080882 | 131 | def found_address_or_data(self, scl, sda): |
7b86f0bc UH |
132 | # Address and data are transmitted MSB-first. |
133 | self.databyte <<= 1 | |
134 | self.databyte |= sda | |
135 | ||
c4975078 BV |
136 | if self.bitcount == 0: |
137 | self.startsample = self.samplenum | |
138 | ||
7b86f0bc | 139 | # Return if we haven't collected all 8 + 1 bits, yet. |
c4975078 | 140 | self.bitcount += 1 |
1b75abfd | 141 | if self.bitcount != 8: |
eb7082c9 | 142 | return |
7b86f0bc | 143 | |
1b75abfd BV |
144 | # We triggered on the ACK/NACK bit, but won't report that until later. |
145 | self.startsample -= 1 | |
146 | ||
eb7082c9 | 147 | # Send raw output annotation before we start shifting out |
1b75abfd | 148 | # read/write and ACK/NACK bits. |
eb7082c9 | 149 | self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]]) |
15969949 | 150 | |
2b716038 | 151 | if self.state == 'FIND ADDRESS': |
7b86f0bc | 152 | # The READ/WRITE bit is only in address bytes, not data bytes. |
bf1c3f4d | 153 | self.wr = 0 if (self.databyte & 1) else 1 |
84b81f1d | 154 | d = self.databyte >> 1 |
2b716038 | 155 | elif self.state == 'FIND DATA': |
7b86f0bc | 156 | d = self.databyte |
15969949 | 157 | |
2b716038 | 158 | if self.state == 'FIND ADDRESS' and self.wr == 1: |
a2d2aff2 | 159 | cmd = 'ADDRESS WRITE' |
2b716038 | 160 | elif self.state == 'FIND ADDRESS' and self.wr == 0: |
a2d2aff2 | 161 | cmd = 'ADDRESS READ' |
2b716038 | 162 | elif self.state == 'FIND DATA' and self.wr == 1: |
a2d2aff2 | 163 | cmd = 'DATA WRITE' |
2b716038 | 164 | elif self.state == 'FIND DATA' and self.wr == 0: |
a2d2aff2 | 165 | cmd = 'DATA READ' |
eb7082c9 | 166 | |
1b75abfd | 167 | self.put(self.out_proto, [cmd, d]) |
1541976f UH |
168 | self.put(self.out_ann, [ANN_SHIFTED, [proto[cmd][0], '0x%02x' % d]]) |
169 | self.put(self.out_ann, [ANN_SHIFTED_SHORT, [proto[cmd][1], '0x%02x' % d]]) | |
7b86f0bc | 170 | |
1b75abfd | 171 | # Done with this packet. |
7b86f0bc | 172 | self.startsample = -1 |
1b75abfd | 173 | self.bitcount = self.databyte = 0 |
2b716038 | 174 | self.state = 'FIND ACK' |
7b86f0bc | 175 | |
1b75abfd BV |
176 | def get_ack(self, scl, sda): |
177 | self.startsample = self.samplenum | |
178 | ack_bit = 'NACK' if (sda == 1) else 'ACK' | |
179 | self.put(self.out_proto, [ack_bit, None]) | |
1541976f UH |
180 | self.put(self.out_ann, [ANN_SHIFTED, [proto[ack_bit][0]]]) |
181 | self.put(self.out_ann, [ANN_SHIFTED_SHORT, [proto[ack_bit][1]]]) | |
1b75abfd BV |
182 | # There could be multiple data bytes in a row, so either find |
183 | # another data byte or a STOP condition next. | |
2b716038 | 184 | self.state = 'FIND DATA' |
7b86f0bc | 185 | |
e5080882 | 186 | def found_stop(self, scl, sda): |
c4975078 | 187 | self.startsample = self.samplenum |
1b75abfd | 188 | self.put(self.out_proto, ['STOP', None]) |
1541976f UH |
189 | self.put(self.out_ann, [ANN_SHIFTED, [proto['STOP'][0]]]) |
190 | self.put(self.out_ann, [ANN_SHIFTED_SHORT, [proto['STOP'][1]]]) | |
7b86f0bc | 191 | |
2b716038 | 192 | self.state = 'FIND START' |
5dd9af5b | 193 | self.is_repeat_start = 0 |
7b86f0bc UH |
194 | self.wr = -1 |
195 | ||
1aef2f93 | 196 | def put(self, output_id, data): |
eb7082c9 | 197 | # Inject sample range into the call up to sigrok. |
c4975078 | 198 | super(Decoder, self).put(self.startsample, self.samplenum, output_id, data) |
1aef2f93 | 199 | |
2b9837d9 | 200 | def decode(self, ss, es, data): |
bc5f5a43 | 201 | for samplenum, (scl, sda) in data: |
c4975078 | 202 | self.samplenum = samplenum |
f39d2404 UH |
203 | |
204 | # First sample: Save SCL/SDA value. | |
205 | if self.oldscl == None: | |
bc5f5a43 BV |
206 | self.oldscl = scl |
207 | self.oldsda = sda | |
ad2dc0de | 208 | continue |
0588ed70 | 209 | |
f39d2404 UH |
210 | # TODO: Wait until the bus is idle (SDA = SCL = 1) first? |
211 | ||
7b86f0bc | 212 | # State machine. |
2b716038 | 213 | if self.state == 'FIND START': |
7b86f0bc | 214 | if self.is_start_condition(scl, sda): |
e5080882 | 215 | self.found_start(scl, sda) |
2b716038 | 216 | elif self.state == 'FIND ADDRESS': |
7b86f0bc | 217 | if self.is_data_bit(scl, sda): |
e5080882 | 218 | self.found_address_or_data(scl, sda) |
2b716038 | 219 | elif self.state == 'FIND DATA': |
7b86f0bc | 220 | if self.is_data_bit(scl, sda): |
e5080882 | 221 | self.found_address_or_data(scl, sda) |
7b86f0bc | 222 | elif self.is_start_condition(scl, sda): |
e5080882 | 223 | self.found_start(scl, sda) |
7b86f0bc | 224 | elif self.is_stop_condition(scl, sda): |
e5080882 | 225 | self.found_stop(scl, sda) |
2b716038 | 226 | elif self.state == 'FIND ACK': |
1b75abfd BV |
227 | if self.is_data_bit(scl, sda): |
228 | self.get_ack(scl, sda) | |
7b86f0bc | 229 | else: |
decde15e | 230 | raise Exception('Invalid state %d' % self.STATE) |
f39d2404 UH |
231 | |
232 | # Save current SDA/SCL values for the next round. | |
233 | self.oldscl = scl | |
234 | self.oldsda = sda | |
235 |