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3bf68998 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
35b380b1 | 3 | ## |
5188abb9 | 4 | ## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de> |
3bf68998 MR |
5 | ## Copyright (C) 2013 Matt Ranostay <mranostay@gmail.com> |
6 | ## | |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
18 | ## along with this program; if not, write to the Free Software | |
19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | ## | |
21 | ||
5188abb9 | 22 | import re |
3bf68998 MR |
23 | import sigrokdecode as srd |
24 | ||
5188abb9 UH |
25 | days_of_week = ( |
26 | 'Sunday', 'Monday', 'Tuesday', 'Wednesday', | |
27 | 'Thursday', 'Friday', 'Saturday', | |
28 | ) | |
29 | ||
30 | regs = ( | |
31 | 'Seconds', 'Minutes', 'Hours', 'Day', 'Date', 'Month', 'Year', | |
32 | 'Control', 'RAM', | |
33 | ) | |
34 | ||
35 | bits = ( | |
36 | 'Clock halt', 'Seconds', 'Reserved', 'Minutes', '12/24 hours', 'AM/PM', | |
37 | 'Hours', 'Day', 'Date', 'Month', 'Year', 'OUT', 'SQWE', 'RS', 'RAM', | |
38 | ) | |
39 | ||
37834eed UH |
40 | rates = { |
41 | 0b00: '1Hz', | |
42 | 0b01: '4096kHz', | |
43 | 0b10: '8192kHz', | |
44 | 0b11: '32768kHz', | |
45 | } | |
46 | ||
00bdc23e UH |
47 | DS1307_I2C_ADDRESS = 0x68 |
48 | ||
5188abb9 UH |
49 | def regs_and_bits(): |
50 | l = [('reg-' + r.lower(), r + ' register') for r in regs] | |
51 | l += [('bit-' + re.sub('\/| ', '-', b).lower(), b + ' bit') for b in bits] | |
52 | return tuple(l) | |
3bf68998 MR |
53 | |
54 | # Return the specified BCD number (max. 8 bits) as integer. | |
55 | def bcd2int(b): | |
56 | return (b & 0x0f) + ((b >> 4) * 10) | |
57 | ||
58 | class Decoder(srd.Decoder): | |
12851357 | 59 | api_version = 2 |
3bf68998 MR |
60 | id = 'ds1307' |
61 | name = 'DS1307' | |
62 | longname = 'Dallas DS1307' | |
63 | desc = 'Realtime clock module protocol.' | |
64 | license = 'gplv2+' | |
65 | inputs = ['i2c'] | |
66 | outputs = ['ds1307'] | |
5188abb9 UH |
67 | annotations = regs_and_bits() + ( |
68 | ('read-datetime', 'Read date/time'), | |
69 | ('write-datetime', 'Write date/time'), | |
70 | ('reg-read', 'Register read'), | |
71 | ('reg-write', 'Register write'), | |
00bdc23e | 72 | ('warnings', 'Warnings'), |
5188abb9 UH |
73 | ) |
74 | annotation_rows = ( | |
75 | ('bits', 'Bits', tuple(range(9, 24))), | |
76 | ('regs', 'Registers', tuple(range(9))), | |
77 | ('date-time', 'Date/time', (24, 25, 26, 27)), | |
00bdc23e | 78 | ('warnings', 'Warnings', (28,)), |
da9bcbd9 | 79 | ) |
3bf68998 MR |
80 | |
81 | def __init__(self, **kwargs): | |
82 | self.state = 'IDLE' | |
83 | self.hours = -1 | |
84 | self.minutes = -1 | |
85 | self.seconds = -1 | |
86 | self.days = -1 | |
87 | self.date = -1 | |
88 | self.months = -1 | |
89 | self.years = -1 | |
5188abb9 | 90 | self.bits = [] |
3bf68998 | 91 | |
8915b346 | 92 | def start(self): |
be465111 | 93 | self.out_ann = self.register(srd.OUTPUT_ANN) |
3bf68998 | 94 | |
3bf68998 MR |
95 | def putx(self, data): |
96 | self.put(self.ss, self.es, self.out_ann, data) | |
97 | ||
5188abb9 UH |
98 | def putd(self, bit1, bit2, data): |
99 | self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data) | |
100 | ||
101 | def putr(self, bit): | |
102 | self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann, | |
103 | [11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']]) | |
104 | ||
105 | def handle_reg_0x00(self, b): # Seconds (0-59) / Clock halt bit | |
106 | self.putd(7, 0, [0, ['Seconds', 'Sec', 'S']]) | |
107 | ch = 1 if (b & (1 << 7)) else 0 | |
108 | self.putd(7, 7, [9, ['Clock halt: %d' % ch, 'Clk hlt: %d' % ch, | |
109 | 'CH: %d' % ch, 'CH']]) | |
110 | s = self.seconds = bcd2int(b & 0x7f) | |
111 | self.putd(6, 0, [10, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s, 'S']]) | |
112 | ||
113 | def handle_reg_0x01(self, b): # Minutes (0-59) | |
114 | self.putd(7, 0, [1, ['Minutes', 'Min', 'M']]) | |
115 | self.putr(7) | |
116 | m = self.minutes = bcd2int(b & 0x7f) | |
117 | self.putd(6, 0, [12, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']]) | |
118 | ||
119 | def handle_reg_0x02(self, b): # Hours (1-12+AM/PM or 0-23) | |
120 | self.putd(7, 0, [2, ['Hours', 'H']]) | |
121 | self.putr(7) | |
122 | ampm_mode = True if (b & (1 << 6)) else False | |
123 | if ampm_mode: | |
124 | self.putd(6, 6, [13, ['12-hour mode', '12h mode', '12h']]) | |
125 | a = 'AM' if (b & (1 << 6)) else 'PM' | |
126 | self.putd(5, 5, [14, [a, a[0]]]) | |
127 | h = self.hours = bcd2int(b & 0x1f) | |
128 | self.putd(4, 0, [15, ['Hour: %d' % h, 'H: %d' % h, 'H']]) | |
129 | else: | |
130 | self.putd(6, 6, [13, ['24-hour mode', '24h mode', '24h']]) | |
131 | h = self.hours = bcd2int(b & 0x3f) | |
132 | self.putd(5, 0, [15, ['Hour: %d' % h, 'H: %d' % h, 'H']]) | |
133 | ||
134 | def handle_reg_0x03(self, b): # Day / day of week (1-7) | |
135 | self.putd(7, 0, [3, ['Day of week', 'Day', 'D']]) | |
136 | for i in (7, 6, 5, 4, 3): | |
137 | self.putr(i) | |
138 | w = self.days = bcd2int(b & 0x07) | |
139 | ws = days_of_week[self.days - 1] | |
140 | self.putd(2, 0, [16, ['Weekday: %s' % ws, 'WD: %s' % ws, 'WD', 'W']]) | |
141 | ||
142 | def handle_reg_0x04(self, b): # Date (1-31) | |
143 | self.putd(7, 0, [4, ['Date', 'D']]) | |
144 | for i in (7, 6): | |
145 | self.putr(i) | |
146 | d = self.date = bcd2int(b & 0x3f) | |
147 | self.putd(5, 0, [17, ['Date: %d' % d, 'D: %d' % d, 'D']]) | |
148 | ||
149 | def handle_reg_0x05(self, b): # Month (1-12) | |
150 | self.putd(7, 0, [5, ['Month', 'Mon', 'M']]) | |
151 | for i in (7, 6, 5): | |
152 | self.putr(i) | |
153 | m = self.months = bcd2int(b & 0x1f) | |
154 | self.putd(4, 0, [18, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']]) | |
155 | ||
156 | def handle_reg_0x06(self, b): # Year (0-99) | |
157 | self.putd(7, 0, [6, ['Year', 'Y']]) | |
158 | y = self.years = bcd2int(b & 0xff) | |
159 | self.years += 2000 | |
160 | self.putd(7, 0, [19, ['Year: %d' % y, 'Y: %d' % y, 'Y']]) | |
3bf68998 MR |
161 | |
162 | def handle_reg_0x07(self, b): # Control Register | |
37834eed UH |
163 | self.putd(7, 0, [7, ['Control', 'Ctrl', 'C']]) |
164 | for i in (6, 5, 3, 2): | |
165 | self.putr(i) | |
166 | o = 1 if (b & (1 << 7)) else 0 | |
167 | s = 1 if (b & (1 << 4)) else 0 | |
168 | s2 = 'en' if (b & (1 << 4)) else 'dis' | |
169 | r = rates[b & 0x03] | |
170 | self.putd(7, 7, [20, ['Output control: %d' % o, | |
171 | 'OUT: %d' % o, 'O: %d' % o, 'O']]) | |
172 | self.putd(4, 4, [21, ['Square wave output: %sabled' % s2, | |
173 | 'SQWE: %sabled' % s2, 'SQWE: %d' % s, 'S: %d' % s, 'S']]) | |
174 | self.putd(1, 0, [22, ['Square wave output rate: %s' % r, | |
175 | 'Square wave rate: %s' % r, 'SQW rate: %s' % r, 'Rate: %s' % r, | |
176 | 'RS: %s' % s, 'RS', 'R']]) | |
3bf68998 | 177 | |
903e9b14 UH |
178 | def handle_reg_0x3f(self, b): # RAM (bytes 0x08-0x3f) |
179 | self.putd(7, 0, [8, ['RAM', 'R']]) | |
180 | self.putd(7, 0, [23, ['SRAM: 0x%02X' % b, '0x%02X' % b]]) | |
181 | ||
53908ef1 UH |
182 | def output_datetime(self, cls, rw): |
183 | # TODO: Handle read/write of only parts of these items. | |
184 | d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % ( | |
185 | days_of_week[self.days - 1], self.date, self.months, | |
186 | self.years, self.hours, self.minutes, self.seconds) | |
187 | self.put(self.block_start_sample, self.es, self.out_ann, | |
188 | [cls, ['%s date/time: %s' % (rw, d)]]) | |
189 | ||
190 | def handle_reg(self, b): | |
191 | r = self.reg if self.reg < 8 else 0x3f | |
192 | fn = getattr(self, 'handle_reg_0x%02x' % r) | |
193 | fn(b) | |
7d747990 UH |
194 | # Honor address auto-increment feature of the DS1307. When the |
195 | # address reaches 0x3f, it will wrap around to address 0. | |
53908ef1 | 196 | self.reg += 1 |
7d747990 UH |
197 | if self.reg > 0x3f: |
198 | self.reg = 0 | |
53908ef1 | 199 | |
00bdc23e UH |
200 | def is_correct_chip(self, addr): |
201 | if addr == DS1307_I2C_ADDRESS: | |
202 | return True | |
203 | self.put(self.block_start_sample, self.es, self.out_ann, | |
204 | [28, ['Ignoring non-DS1307 data (slave 0x%02X)' % addr]]) | |
205 | return False | |
206 | ||
3bf68998 MR |
207 | def decode(self, ss, es, data): |
208 | cmd, databyte = data | |
209 | ||
5188abb9 UH |
210 | # Collect the 'BITS' packet, then return. The next packet is |
211 | # guaranteed to belong to these bits we just stored. | |
212 | if cmd == 'BITS': | |
213 | self.bits = databyte | |
214 | return | |
215 | ||
00197484 | 216 | # Store the start/end samples of this I²C packet. |
3bf68998 MR |
217 | self.ss, self.es = ss, es |
218 | ||
219 | # State machine. | |
220 | if self.state == 'IDLE': | |
00197484 | 221 | # Wait for an I²C START condition. |
3bf68998 MR |
222 | if cmd != 'START': |
223 | return | |
224 | self.state = 'GET SLAVE ADDR' | |
225 | self.block_start_sample = ss | |
226 | elif self.state == 'GET SLAVE ADDR': | |
227 | # Wait for an address write operation. | |
3bf68998 MR |
228 | if cmd != 'ADDRESS WRITE': |
229 | return | |
00bdc23e UH |
230 | if not self.is_correct_chip(databyte): |
231 | self.state = 'IDLE' | |
232 | return | |
3bf68998 MR |
233 | self.state = 'GET REG ADDR' |
234 | elif self.state == 'GET REG ADDR': | |
235 | # Wait for a data write (master selects the slave register). | |
236 | if cmd != 'DATA WRITE': | |
237 | return | |
238 | self.reg = databyte | |
239 | self.state = 'WRITE RTC REGS' | |
240 | elif self.state == 'WRITE RTC REGS': | |
53908ef1 | 241 | # If we see a Repeated Start here, it's an RTC read. |
3bf68998 MR |
242 | if cmd == 'START REPEAT': |
243 | self.state = 'READ RTC REGS' | |
244 | return | |
245 | # Otherwise: Get data bytes until a STOP condition occurs. | |
246 | if cmd == 'DATA WRITE': | |
53908ef1 | 247 | self.handle_reg(databyte) |
3bf68998 | 248 | elif cmd == 'STOP': |
53908ef1 | 249 | self.output_datetime(25, 'Written') |
3bf68998 | 250 | self.state = 'IDLE' |
3bf68998 MR |
251 | elif self.state == 'READ RTC REGS': |
252 | # Wait for an address read operation. | |
00bdc23e UH |
253 | if cmd != 'ADDRESS READ': |
254 | return | |
255 | if not self.is_correct_chip(databyte): | |
256 | self.state = 'IDLE' | |
3bf68998 | 257 | return |
00bdc23e | 258 | self.state = 'READ RTC REGS2' |
3bf68998 MR |
259 | elif self.state == 'READ RTC REGS2': |
260 | if cmd == 'DATA READ': | |
53908ef1 | 261 | self.handle_reg(databyte) |
3bf68998 | 262 | elif cmd == 'STOP': |
53908ef1 | 263 | self.output_datetime(24, 'Read') |
3bf68998 | 264 | self.state = 'IDLE' |