2 * This file is part of the sigrok-firmware-fx2lafw project.
4 * Copyright (C) 2009 Ubixum, Inc.
5 * Copyright (C) 2015 Jochen Hoenicke
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include <fx2macros.h>
23 #include <autovector.h>
27 #define SET_ANALOG_MODE() PA7 = 1
29 /* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
30 /* Note: There's no PE2 as IOE is not bit-addressable (see TRM 15.2). */
31 #define TOGGLE_CALIBRATION_PIN() IOE = IOE ^ 0x04
33 #define LED_CLEAR() NOP
34 #define LED_GREEN() NOP
37 /* CTLx pin index (IFCLK, ADC clock input). */
40 #define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
41 #define OE_CTL (((1 << CTL_BIT) << 4) | (1 << CTL_BIT)) /* OEx = CTLx = 1 */
43 /* Change to support as many interfaces as you need. */
44 static BYTE altiface = 0;
46 static volatile WORD ledcounter = 0;
48 static volatile __bit dosud = FALSE;
49 static volatile __bit dosuspend = FALSE;
51 extern __code BYTE highspd_dscr;
52 extern __code BYTE fullspd_dscr;
54 void resume_isr(void) __interrupt RESUME_ISR
59 void sudav_isr(void) __interrupt SUDAV_ISR
65 void usbreset_isr(void) __interrupt USBRESET_ISR
67 handle_hispeed(FALSE);
71 void hispeed_isr(void) __interrupt HISPEED_ISR
77 void suspend_isr(void) __interrupt SUSPEND_ISR
83 void timer2_isr(void) __interrupt TF2_ISR
85 TOGGLE_CALIBRATION_PIN();
87 if (ledcounter && (--ledcounter == 0))
94 * The gain stage is 2 stage approach. -6dB and -20dB on the first stage
95 * (attentuator). The second stage is then doing the gain by 3 different
96 * resistor values switched into the feedback loop.
99 * PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
100 * PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
101 * PC1=1; PC2=1; PC3= 0 -> Gain x0.4 = -8dB
102 * PC1=0; PC2=0; PC3= 0 -> Gain x0.5 = -6dB
103 * PC1=0; PC2=0; PC3= 1 -> Gain x1 = 0dB
104 * PC1=0; PC2=1; PC3= 0 -> Gain x2 = +6dB
107 * PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB
108 * PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
109 * PE1=1; PC4=1; PC5= 0 -> Gain x0.4 = -8dB
110 * PE1=0; PC4=0; PC5= 0 -> Gain x0.5 = -6dB
111 * PE1=0; PC4=0; PC5= 1 -> Gain x1 = 0dB
112 * PE1=0; PC4=1; PC5= 0 -> Gain x2 = +6dB
114 static BOOL set_voltage(BYTE channel, BYTE val)
116 BYTE bits_C, bit_E, mask_C, mask_E;
141 } else if (channel == 1) {
171 IOC = (IOC & ~mask_C) | (bits_C & mask_C);
172 IOE = (IOE & ~mask_E) | (bit_E & mask_E);
178 * Each LSB in the nibble of the byte controls the coupling per channel.
180 * Setting PE3 disables AC coupling capacitor on CH0.
181 * Setting PE0 disables AC coupling capacitor on CH1.
183 static void set_coupling(BYTE coupling_cfg)
185 if (coupling_cfg & 0x01)
190 if (coupling_cfg & 0x10)
196 static BOOL set_numchannels(BYTE numchannels)
198 if (numchannels == 1 || numchannels == 2) {
199 BYTE fifocfg = 7 + numchannels;
200 EP2FIFOCFG = fifocfg;
201 EP6FIFOCFG = fifocfg;
208 static void clear_fifo(void)
221 static void stop_sampling(void)
225 INPKTEND = (altiface == 0) ? 6 : 2;
228 static void start_sampling(void)
236 for (i = 0; i < 1000; i++);
238 while (!(GPIFTRIG & 0x80))
245 GPIFTRIG = (altiface == 0) ? 6 : 4;
247 /* Set green LED, don't clear LED afterwards (ledcounter = 0). */
252 static void select_interface(BYTE alt)
254 const BYTE *pPacketSize = \
255 ((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
256 + (9 + (16 * alt) + 9 + 4);
265 EP6AUTOINLENL = pPacketSize[0];
266 EP6AUTOINLENH = pPacketSize[1];
272 EP2AUTOINLENL = pPacketSize[0];
273 EP2AUTOINLENH = pPacketSize[1] & 0x7;
274 EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
278 static const struct samplerate_info {
287 { 48, 0x80, 0, 3, 0, 0x00, 0xea },
288 { 30, 0x80, 0, 3, 0, 0x00, 0xaa },
289 { 24, 1, 0, 2, 1, OUT0, 0xea },
290 { 16, 1, 1, 2, 0, OUT0, 0xea },
291 { 15, 1, 0, 2, 1, OUT0, 0xaa },
292 { 12, 2, 1, 2, 0, OUT0, 0xea },
293 { 11, 1, 1, 2, 0, OUT0, 0xaa },
294 { 8, 3, 2, 2, 0, OUT0, 0xea },
295 { 6, 2, 2, 2, 0, OUT0, 0xaa },
296 { 5, 3, 2, 2, 0, OUT0, 0xaa },
297 { 4, 6, 5, 2, 0, OUT0, 0xea },
298 { 3, 5, 4, 2, 0, OUT0, 0xaa },
299 { 2, 12, 11, 2, 0, OUT0, 0xea },
300 { 1, 24, 23, 2, 0, OUT0, 0xea },
301 { 50, 48, 47, 2, 0, OUT0, 0xea },
302 { 20, 120, 119, 2, 0, OUT0, 0xea },
303 { 10, 240, 239, 2, 0, OUT0, 0xea },
306 static BOOL set_samplerate(BYTE rate)
310 while (samplerates[i].rate != rate) {
312 if (i == sizeof(samplerates) / sizeof(samplerates[0]))
316 IFCONFIG = samplerates[i].ifcfg;
319 AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
323 * The program for low-speed, e.g. 1 MHz, is:
324 * wait 24, CTLx=0, FIFO
328 * The program for 24 MHz is:
329 * wait 1, CTLx=0, FIFO
332 * The program for 30/48 MHz is:
333 * jump 0, CTLx=Z, FIFO, LOOP
335 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
338 /* LENGTH / BRANCH 0-7 */
339 EXTAUTODAT2 = samplerates[i].wait0;
340 EXTAUTODAT2 = samplerates[i].wait1;
349 EXTAUTODAT2 = samplerates[i].opc0;
350 EXTAUTODAT2 = samplerates[i].opc1;
351 EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
359 EXTAUTODAT2 = samplerates[i].out0;
360 EXTAUTODAT2 = OE_CTL;
361 EXTAUTODAT2 = OE_CTL;
368 /* LOGIC FUNCTION 0-7 */
378 for (i = 0; i < 96; i++)
384 static BOOL set_calibration_pulse(BYTE fs)
388 RCAP2L = -10000 & 0xff;
389 RCAP2H = (-10000 & 0xff00) >> 8;
392 RCAP2L = -1000 & 0xff;
393 RCAP2H = (-1000 & 0xff00) >> 8;
396 RCAP2L = (BYTE)(-100 & 0xff);
400 RCAP2L = (BYTE)(-20 & 0xff);
408 /* Set *alt_ifc to the current alt interface for ifc. */
409 BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
419 * Return TRUE if you set the interface requested.
421 * Note: This function should reconfigure and reset the endpoints
422 * according to the interface descriptors you provided.
424 BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
427 select_interface(alt_ifc);
432 BYTE handle_get_configuration(void)
434 /* We only support configuration 0. */
438 BOOL handle_set_configuration(BYTE cfg)
440 /* We only support configuration 0. */
446 BOOL handle_vendorcommand(BYTE cmd)
450 /* Set red LED, clear after timeout. */
454 /* Clear EP0BCH/L for each valid command. */
455 if (cmd >= 0xe0 && cmd <= 0xe6) {
458 while (EP0CS & bmEPBUSY);
464 set_voltage(cmd - 0xe0, EP0BUF[0]);
467 set_samplerate(EP0BUF[0]);
474 set_numchannels(EP0BUF[0]);
477 set_coupling(EP0BUF[0]);
480 set_calibration_pulse(EP0BUF[0]);
484 return FALSE; /* Not handled by handlers. */
487 static void init(void)
494 /* In idle mode tristate all outputs. */
495 GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
496 GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
498 GPIFREADYSTAT = 0x00;
509 static void main(void)
516 /* Set up interrupts. */
525 /* Global (8051) interrupt enable. */
529 RCAP2L = -1000 & 0xff;
530 RCAP2H = (-1000 & 0xff00) >> 8;
555 /* Make sure ext wakeups are cleared. */
556 WAKEUPCS |= bmWU | bmWU2;
568 } while (!remote_wakeup_allowed && REMOTE_WAKEUP());
570 /* Resume (TRM 6.4). */
571 if (REMOTE_WAKEUP()) {
573 USBCS |= bmSIGRESUME;
575 USBCS &= ~bmSIGRESUME;