[sigrok-firmware-fx2lafw.git] / sainsmart_dds120.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

#define SET_ANALOG_MODE() PA7 = 1

/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
/* Note: There's no PE2 as IOE is not bit-addressable (see TRM 15.2). */
#define TOGGLE_CALIBRATION_PIN() IOE = IOE ^ 0x04

#define LED_CLEAR() NOP
#define LED_GREEN() NOP
#define LED_RED()   NOP

/* CTLx pin index (IFCLK, ADC clock input). */
#define CTL_BIT 2

#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
#define OE_CTL (((1 << CTL_BIT) << 4) | (1 << CTL_BIT)) /* OEx = CTLx = 1 */

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile WORD ledcounter = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	TOGGLE_CALIBRATION_PIN();

	if (ledcounter && (--ledcounter == 0))
		LED_CLEAR();

	TF2 = 0;
}

/**
 * The gain stage is 2 stage approach. -6dB and -20dB on the first stage
 * (attentuator). The second stage is then doing the gain by 3 different
 * resistor values switched into the feedback loop.
 *
 * #Channel 0:
 * PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
 * PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
 * PC1=1; PC2=1; PC3= 0 -> Gain x0.4 =  -8dB
 * PC1=0; PC2=0; PC3= 0 -> Gain x0.5 =  -6dB
 * PC1=0; PC2=0; PC3= 1 -> Gain x1   =   0dB
 * PC1=0; PC2=1; PC3= 0 -> Gain x2   =  +6dB
 *
 * #Channel 1:
 * PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB 
 * PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
 * PE1=1; PC4=1; PC5= 0 -> Gain x0.4 =  -8dB
 * PE1=0; PC4=0; PC5= 0 -> Gain x0.5 =  -6dB
 * PE1=0; PC4=0; PC5= 1 -> Gain x1   =   0dB
 * PE1=0; PC4=1; PC5= 0 -> Gain x2   =  +6dB
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits_C, bit_E, mask_C, mask_E;

	if (channel == 0) {
		mask_C = 0x0E;
		mask_E = 0x00;
		bit_E = 0;
		switch (val) {
		case 1:
			bits_C = 0x02;
			break;
		case 2:
			bits_C = 0x06;
			break;
		case 5:
			bits_C = 0x00;
			break;
		case 10:
			bits_C = 0x04;
			break;
		case 20:
			bits_C = 0x08;
			break;
		default:
			return FALSE;
		}
	} else if (channel == 1) {
		mask_C = 0x30;
		mask_E = 0x02;
		switch (val) {
		case 1:
			bits_C = 0x00;
			bit_E = 0x02; 
			break;
		case 2:
			bits_C = 0x10;
			bit_E = 0x02; 
			break;
		case 5:
			bits_C = 0x00;
			bit_E = 0x00; 
			break;
		case 10:
			bits_C = 0x10;
			bit_E = 0x00; 
			break;
		case 20:
			bits_C = 0x20;
			bit_E = 0x00; 
			break;
		default:
			return FALSE;
		}
	} else {
		return FALSE;
	}
	IOC = (IOC & ~mask_C) | (bits_C & mask_C);
	IOE = (IOE & ~mask_E) | (bit_E & mask_E);
		
	return TRUE;
}

/**
 * Each LSB in the nibble of the byte controls the coupling per channel.
 *
 * Setting PE3 disables AC coupling capacitor on CH0.
 * Setting PE0 disables AC coupling capacitor on CH1.
 */
static void set_coupling(BYTE coupling_cfg)
{
	if (coupling_cfg & 0x01)
		IOE |= 0x08;
	else
		IOE &= ~0x08;

	if (coupling_cfg & 0x10)
		IOE |= 0x01;
	else
		IOE &= ~0x01;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	SET_ANALOG_MODE();

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
	LED_GREEN();
	ledcounter = 0;
}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, OUT0, 0xea },
	{ 16,    1,   1, 2, 0, OUT0, 0xea },
	{ 15,    1,   0, 2, 1, OUT0, 0xaa },
	{ 12,    2,   1, 2, 0, OUT0, 0xea },
	{ 11,    1,   1, 2, 0, OUT0, 0xaa },
	{  8,    3,   2, 2, 0, OUT0, 0xea },
	{  6,    2,   2, 2, 0, OUT0, 0xaa },
	{  5,    3,   2, 2, 0, OUT0, 0xaa },
	{  4,    6,   5, 2, 0, OUT0, 0xea },
	{  3,    5,   4, 2, 0, OUT0, 0xaa },
	{  2,   12,  11, 2, 0, OUT0, 0xea },
	{  1,   24,  23, 2, 0, OUT0, 0xea },
	{ 50,   48,  47, 2, 0, OUT0, 0xea },
	{ 20,  120, 119, 2, 0, OUT0, 0xea },
	{ 10,  240, 239, 2, 0, OUT0, 0xea },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTLx=0, FIFO
	 * wait 23, CTLx=1
	 * jump 0, CTLx=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTLx=0, FIFO
	 * jump 0, CTLx=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTLx=Z, FIFO, LOOP
	 *
	 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

static BOOL set_calibration_pulse(BYTE fs)
{
	switch (fs) {
	case 0:		// 100Hz
		RCAP2L = -10000 & 0xff;
		RCAP2H = (-10000 & 0xff00) >> 8;
		return TRUE;
	case 1:		// 1kHz
		RCAP2L = -1000 & 0xff;
		RCAP2H = (-1000 & 0xff00) >> 8;
		return TRUE;
	case 10:	// 1kHz
		RCAP2L = (BYTE)(-100 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	case 50:	// 50kHz
		RCAP2L = (BYTE)(-20 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	default:
		return FALSE;
	}
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Set red LED, clear after timeout. */
	LED_RED();
	ledcounter = 1000;

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe6) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	case 0xe5:
		set_coupling(EP0BUF[0]);
		return TRUE;
	case 0xe6:
		set_calibration_pulse(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	SET_ANALOG_MODE();

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -1000 & 0xff;
	RCAP2H = (-1000 & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE_UNCOND();

	PORTECFG = 0;
	PORTCCFG = 0;
	PORTACFG = 0;
	OEE = 0xff;
	OEC = 0xff;
	OEA = 0xff;

	SET_ANALOG_MODE();

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU | bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
ce1d0a86 BL	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
040a6eae	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
ce1d0a86 BL	19	*/
	20
	21	#include <fx2macros.h>
	22	#include <fx2ints.h>
	23	#include <autovector.h>
	24	#include <delay.h>
	25	#include <setupdat.h>
	26
be6d306d UH	27	#define SET_ANALOG_MODE() PA7 = 1
be6d306d UH	28
e583c3fc UH	29	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
	30	/* Note: There's no PE2 as IOE is not bit-addressable (see TRM 15.2). */
	31	#define TOGGLE_CALIBRATION_PIN() IOE = IOE ^ 0x04
	32
65b34f7e UH	33	#define LED_CLEAR() NOP
	34	#define LED_GREEN() NOP
	35	#define LED_RED() NOP
	36
e1c5ba21 UH	37	/* CTLx pin index (IFCLK, ADC clock input). */
	38	#define CTL_BIT 2
	39
	40	#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
	41	#define OE_CTL (((1 << CTL_BIT) << 4) \| (1 << CTL_BIT)) /* OEx = CTLx = 1 */
	42
ce1d0a86 BL	43	/* Change to support as many interfaces as you need. */
	44	static BYTE altiface = 0;
	45
65b34f7e UH	46	static volatile WORD ledcounter = 0;
65b34f7e UH	47
ce1d0a86 BL	48	static volatile __bit dosud = FALSE;
	49	static volatile __bit dosuspend = FALSE;
	50
	51	extern __code BYTE highspd_dscr;
	52	extern __code BYTE fullspd_dscr;
	53
	54	void resume_isr(void) __interrupt RESUME_ISR
	55	{
	56	CLEAR_RESUME();
	57	}
	58
	59	void sudav_isr(void) __interrupt SUDAV_ISR
	60	{
	61	dosud = TRUE;
	62	CLEAR_SUDAV();
	63	}
	64
	65	void usbreset_isr(void) __interrupt USBRESET_ISR
	66	{
	67	handle_hispeed(FALSE);
	68	CLEAR_USBRESET();
	69	}
	70
	71	void hispeed_isr(void) __interrupt HISPEED_ISR
	72	{
	73	handle_hispeed(TRUE);
	74	CLEAR_HISPEED();
	75	}
	76
	77	void suspend_isr(void) __interrupt SUSPEND_ISR
	78	{
	79	dosuspend = TRUE;
	80	CLEAR_SUSPEND();
	81	}
	82
	83	void timer2_isr(void) __interrupt TF2_ISR
	84	{
e583c3fc UH	85	TOGGLE_CALIBRATION_PIN();
e583c3fc UH	86
65b34f7e UH	87	if (ledcounter && (--ledcounter == 0))
	88	LED_CLEAR();
	89
ce1d0a86 BL	90	TF2 = 0;
	91	}
	92
	93	/**
3968bbfb UH	94	* The gain stage is 2 stage approach. -6dB and -20dB on the first stage
	95	* (attentuator). The second stage is then doing the gain by 3 different
	96	* resistor values switched into the feedback loop.
	97	*
ce1d0a86 BL	98	* #Channel 0:
	99	* PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
	100	* PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
	101	* PC1=1; PC2=1; PC3= 0 -> Gain x0.4 = -8dB
	102	* PC1=0; PC2=0; PC3= 0 -> Gain x0.5 = -6dB
	103	* PC1=0; PC2=0; PC3= 1 -> Gain x1 = 0dB
	104	* PC1=0; PC2=1; PC3= 0 -> Gain x2 = +6dB
3968bbfb	105	*
ce1d0a86 BL	106	* #Channel 1:
	107	* PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB
	108	* PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
	109	* PE1=1; PC4=1; PC5= 0 -> Gain x0.4 = -8dB
	110	* PE1=0; PC4=0; PC5= 0 -> Gain x0.5 = -6dB
	111	* PE1=0; PC4=0; PC5= 1 -> Gain x1 = 0dB
	112	* PE1=0; PC4=1; PC5= 0 -> Gain x2 = +6dB
	113	*/
	114	static BOOL set_voltage(BYTE channel, BYTE val)
	115	{
	116	BYTE bits_C, bit_E, mask_C, mask_E;
	117
	118	if (channel == 0) {
	119	mask_C = 0x0E;
	120	mask_E = 0x00;
	121	bit_E = 0;
	122	switch (val) {
	123	case 1:
	124	bits_C = 0x02;
	125	break;
	126	case 2:
	127	bits_C = 0x06;
	128	break;
	129	case 5:
	130	bits_C = 0x00;
	131	break;
	132	case 10:
	133	bits_C = 0x04;
	134	break;
	135	case 20:
	136	bits_C = 0x08;
	137	break;
	138	default:
	139	return FALSE;
	140	}
	141	} else if (channel == 1) {
	142	mask_C = 0x30;
	143	mask_E = 0x02;
	144	switch (val) {
	145	case 1:
	146	bits_C = 0x00;
	147	bit_E = 0x02;
	148	break;
	149	case 2:
	150	bits_C = 0x10;
	151	bit_E = 0x02;
	152	break;
	153	case 5:
	154	bits_C = 0x00;
	155	bit_E = 0x00;
	156	break;
	157	case 10:
	158	bits_C = 0x10;
	159	bit_E = 0x00;
	160	break;
	161	case 20:
	162	bits_C = 0x20;
	163	bit_E = 0x00;
	164	break;
	165	default:
	166	return FALSE;
	167	}
	168	} else {
	169	return FALSE;
170	}
171	IOC = (IOC & ~mask_C) \| (bits_C & mask_C);
172	IOE = (IOE & ~mask_E) \| (bit_E & mask_E);
173
174	return TRUE;
175	}
176
75ad0fa5 BL	177	/**
	178	* Each LSB in the nibble of the byte controls the coupling per channel.
	179	*
	180	* Setting PE3 disables AC coupling capacitor on CH0.
	181	* Setting PE0 disables AC coupling capacitor on CH1.
	182	*/
	183	static void set_coupling(BYTE coupling_cfg)
	184	{
	185	if (coupling_cfg & 0x01)
	186	IOE \|= 0x08;
	187	else
	188	IOE &= ~0x08;
	189
	190	if (coupling_cfg & 0x10)
	191	IOE \|= 0x01;
	192	else
	193	IOE &= ~0x01;
	194	}
	195
ce1d0a86 BL	196	static BOOL set_numchannels(BYTE numchannels)
	197	{
	198	if (numchannels == 1 \|\| numchannels == 2) {
	199	BYTE fifocfg = 7 + numchannels;
	200	EP2FIFOCFG = fifocfg;
	201	EP6FIFOCFG = fifocfg;
	202	return TRUE;
	203	}
	204
	205	return FALSE;
	206	}
	207
	208	static void clear_fifo(void)
	209	{
	210	GPIFABORT = 0xff;
	211	SYNCDELAY3;
	212	FIFORESET = 0x80;
	213	SYNCDELAY3;
	214	FIFORESET = 0x82;
	215	SYNCDELAY3;
	216	FIFORESET = 0x86;
	217	SYNCDELAY3;
	218	FIFORESET = 0;
	219	}
	220
	221	static void stop_sampling(void)
	222	{
	223	GPIFABORT = 0xff;
	224	SYNCDELAY3;
	225	INPKTEND = (altiface == 0) ? 6 : 2;
	226	}
	227
	228	static void start_sampling(void)
	229	{
	230	int i;
	231
be6d306d UH	232	SET_ANALOG_MODE();
be6d306d UH	233
ce1d0a86 BL	234	clear_fifo();
	235
	236	for (i = 0; i < 1000; i++);
	237
	238	while (!(GPIFTRIG & 0x80))
	239	;
	240
	241	SYNCDELAY3;
	242	GPIFTCB1 = 0x28;
	243	SYNCDELAY3;
	244	GPIFTCB0 = 0;
	245	GPIFTRIG = (altiface == 0) ? 6 : 4;
	246
65b34f7e UH	247	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
	248	LED_GREEN();
	249	ledcounter = 0;
ce1d0a86 BL	250	}
	251
	252	static void select_interface(BYTE alt)
	253	{
	254	const BYTE *pPacketSize = \
	255	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
	256	+ (9 + (16 * alt) + 9 + 4);
	257
	258	altiface = alt;
	259
	260	if (alt == 0) {
	261	/* Bulk on EP6. */
	262	EP2CFG = 0x00;
	263	EP6CFG = 0xe0;
	264	EP6GPIFFLGSEL = 1;
	265	EP6AUTOINLENL = pPacketSize[0];
	266	EP6AUTOINLENH = pPacketSize[1];
	267	} else {
	268	/* Iso on EP2. */
	269	EP2CFG = 0xd8;
	270	EP6CFG = 0x00;
	271	EP2GPIFFLGSEL = 1;
	272	EP2AUTOINLENL = pPacketSize[0];
	273	EP2AUTOINLENH = pPacketSize[1] & 0x7;
	274	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	275	}
	276	}
	277
	278	static const struct samplerate_info {
	279	BYTE rate;
	280	BYTE wait0;
	281	BYTE wait1;
	282	BYTE opc0;
	283	BYTE opc1;
	284	BYTE out0;
	285	BYTE ifcfg;
	286	} samplerates[] = {
	287	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
	288	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
e1c5ba21 UH	289	{ 24, 1, 0, 2, 1, OUT0, 0xea },
	290	{ 16, 1, 1, 2, 0, OUT0, 0xea },
	291	{ 15, 1, 0, 2, 1, OUT0, 0xaa },
	292	{ 12, 2, 1, 2, 0, OUT0, 0xea },
	293	{ 11, 1, 1, 2, 0, OUT0, 0xaa },
	294	{ 8, 3, 2, 2, 0, OUT0, 0xea },
	295	{ 6, 2, 2, 2, 0, OUT0, 0xaa },
	296	{ 5, 3, 2, 2, 0, OUT0, 0xaa },
	297	{ 4, 6, 5, 2, 0, OUT0, 0xea },
	298	{ 3, 5, 4, 2, 0, OUT0, 0xaa },
	299	{ 2, 12, 11, 2, 0, OUT0, 0xea },
	300	{ 1, 24, 23, 2, 0, OUT0, 0xea },
	301	{ 50, 48, 47, 2, 0, OUT0, 0xea },
	302	{ 20, 120, 119, 2, 0, OUT0, 0xea },
	303	{ 10, 240, 239, 2, 0, OUT0, 0xea },
ce1d0a86 BL	304	};
	305
	306	static BOOL set_samplerate(BYTE rate)
	307	{
	308	BYTE i = 0;
	309
	310	while (samplerates[i].rate != rate) {
	311	i++;
	312	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	313	return FALSE;
	314	}
	315
	316	IFCONFIG = samplerates[i].ifcfg;
	317
	318	AUTOPTRSETUP = 7;
24373950	319	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
ce1d0a86 BL	320	AUTOPTRL2 = 0x00;
	321
	322	/*
	323	* The program for low-speed, e.g. 1 MHz, is:
3968bbfb UH	324	* wait 24, CTLx=0, FIFO
	325	* wait 23, CTLx=1
	326	* jump 0, CTLx=1
ce1d0a86 BL	327	*
ce1d0a86 BL	328	* The program for 24 MHz is:
3968bbfb UH	329	* wait 1, CTLx=0, FIFO
3968bbfb UH	330	* jump 0, CTLx=1
ce1d0a86 BL	331	*
ce1d0a86 BL	332	* The program for 30/48 MHz is:
3968bbfb UH	333	* jump 0, CTLx=Z, FIFO, LOOP
	334	*
	335	* (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
ce1d0a86 BL	336	*/
ce1d0a86 BL	337
24373950	338	/* LENGTH / BRANCH 0-7 */
ce1d0a86 BL	339	EXTAUTODAT2 = samplerates[i].wait0;
	340	EXTAUTODAT2 = samplerates[i].wait1;
	341	EXTAUTODAT2 = 1;
	342	EXTAUTODAT2 = 0;
	343	EXTAUTODAT2 = 0;
	344	EXTAUTODAT2 = 0;
	345	EXTAUTODAT2 = 0;
	346	EXTAUTODAT2 = 0;
	347
24373950	348	/* OPCODE 0-7 */
ce1d0a86 BL	349	EXTAUTODAT2 = samplerates[i].opc0;
ce1d0a86 BL	350	EXTAUTODAT2 = samplerates[i].opc1;
24373950	351	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
ce1d0a86 BL	352	EXTAUTODAT2 = 0;
	353	EXTAUTODAT2 = 0;
	354	EXTAUTODAT2 = 0;
	355	EXTAUTODAT2 = 0;
	356	EXTAUTODAT2 = 0;
	357
24373950	358	/* OUTPUT 0-7 */
ce1d0a86	359	EXTAUTODAT2 = samplerates[i].out0;
e1c5ba21 UH	360	EXTAUTODAT2 = OE_CTL;
e1c5ba21 UH	361	EXTAUTODAT2 = OE_CTL;
24373950 UH	362	EXTAUTODAT2 = 0;
	363	EXTAUTODAT2 = 0;
	364	EXTAUTODAT2 = 0;
	365	EXTAUTODAT2 = 0;
	366	EXTAUTODAT2 = 0;
ce1d0a86	367
24373950	368	/* LOGIC FUNCTION 0-7 */
ce1d0a86 BL	369	EXTAUTODAT2 = 0;
	370	EXTAUTODAT2 = 0;
	371	EXTAUTODAT2 = 0;
	372	EXTAUTODAT2 = 0;
	373	EXTAUTODAT2 = 0;
	374	EXTAUTODAT2 = 0;
	375	EXTAUTODAT2 = 0;
	376	EXTAUTODAT2 = 0;
	377
	378	for (i = 0; i < 96; i++)
	379	EXTAUTODAT2 = 0;
	380
	381	return TRUE;
	382	}
	383
a425fae9 BL	384	static BOOL set_calibration_pulse(BYTE fs)
	385	{
	386	switch (fs) {
	387	case 0: // 100Hz
	388	RCAP2L = -10000 & 0xff;
386296a7	389	RCAP2H = (-10000 & 0xff00) >> 8;
a425fae9 BL	390	return TRUE;
	391	case 1: // 1kHz
	392	RCAP2L = -1000 & 0xff;
386296a7	393	RCAP2H = (-1000 & 0xff00) >> 8;
a425fae9 BL	394	return TRUE;
a425fae9 BL	395	case 10: // 1kHz
386296a7	396	RCAP2L = (BYTE)(-100 & 0xff);
a425fae9 BL	397	RCAP2H = 0xff;
	398	return TRUE;
	399	case 50: // 50kHz
386296a7	400	RCAP2L = (BYTE)(-20 & 0xff);
a425fae9 BL	401	RCAP2H = 0xff;
	402	return TRUE;
	403	default:
	404	return FALSE;
	405	}
	406	}
	407
ce1d0a86 BL	408	/* Set alt_ifc to the current alt interface for ifc. /
	409	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	410	{
	411	(void)ifc;
	412
	413	*alt_ifc = altiface;
	414
	415	return TRUE;
	416	}
	417
	418	/*
	419	* Return TRUE if you set the interface requested.
	420	*
	421	* Note: This function should reconfigure and reset the endpoints
	422	* according to the interface descriptors you provided.
	423	*/
	424	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	425	{
	426	if (ifc == 0)
	427	select_interface(alt_ifc);
	428
	429	return TRUE;
	430	}
	431
	432	BYTE handle_get_configuration(void)
	433	{
	434	/* We only support configuration 0. */
	435	return 0;
	436	}
	437
	438	BOOL handle_set_configuration(BYTE cfg)
	439	{
	440	/* We only support configuration 0. */
	441	(void)cfg;
	442
	443	return TRUE;
	444	}
	445
	446	BOOL handle_vendorcommand(BYTE cmd)
	447	{
	448	stop_sampling();
	449
65b34f7e UH	450	/* Set red LED, clear after timeout. */
	451	LED_RED();
	452	ledcounter = 1000;
	453
ce1d0a86	454	/* Clear EP0BCH/L for each valid command. */
a425fae9	455	if (cmd >= 0xe0 && cmd <= 0xe6) {
ce1d0a86 BL	456	EP0BCH = 0;
	457	EP0BCL = 0;
	458	while (EP0CS & bmEPBUSY);
	459	}
	460
	461	switch (cmd) {
	462	case 0xe0:
	463	case 0xe1:
	464	set_voltage(cmd - 0xe0, EP0BUF[0]);
	465	return TRUE;
	466	case 0xe2:
	467	set_samplerate(EP0BUF[0]);
	468	return TRUE;
	469	case 0xe3:
	470	if (EP0BUF[0] == 1)
	471	start_sampling();
	472	return TRUE;
	473	case 0xe4:
	474	set_numchannels(EP0BUF[0]);
	475	return TRUE;
75ad0fa5 BL	476	case 0xe5:
	477	set_coupling(EP0BUF[0]);
	478	return TRUE;
a425fae9 BL	479	case 0xe6:
	480	set_calibration_pulse(EP0BUF[0]);
	481	return TRUE;
ce1d0a86 BL	482	}
	483
	484	return FALSE; /* Not handled by handlers. */
	485	}
	486
	487	static void init(void)
	488	{
	489	EP4CFG = 0;
	490	EP8CFG = 0;
	491
be6d306d UH	492	SET_ANALOG_MODE();
be6d306d UH	493
ce1d0a86	494	/* In idle mode tristate all outputs. */
24373950 UH	495	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
24373950 UH	496	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
ce1d0a86 BL	497	GPIFWFSELECT = 0x00;
	498	GPIFREADYSTAT = 0x00;
	499
	500	stop_sampling();
	501
	502	set_voltage(0, 1);
	503	set_voltage(1, 1);
	504	set_samplerate(1);
	505	set_numchannels(2);
	506	select_interface(0);
	507	}
	508
	509	static void main(void)
	510	{
	511	/* Save energy. */
	512	SETCPUFREQ(CLK_12M);
	513
	514	init();
	515
	516	/* Set up interrupts. */
	517	USE_USB_INTS();
	518
	519	ENABLE_SUDAV();
	520	ENABLE_USBRESET();
	521	ENABLE_HISPEED();
	522	ENABLE_SUSPEND();
	523	ENABLE_RESUME();
	524
	525	/* Global (8051) interrupt enable. */
	526	EA = 1;
	527
	528	/* Init timer2. */
	529	RCAP2L = -1000 & 0xff;
386296a7	530	RCAP2H = (-1000 & 0xff00) >> 8;
ce1d0a86 BL	531	T2CON = 0;
	532	ET2 = 1;
	533	TR2 = 1;
	534
	535	RENUMERATE_UNCOND();
	536
4d971e01	537	PORTECFG = 0;
ce1d0a86 BL	538	PORTCCFG = 0;
ce1d0a86 BL	539	PORTACFG = 0;
4d971e01	540	OEE = 0xff;
ce1d0a86	541	OEC = 0xff;
4d971e01	542	OEA = 0xff;
ce1d0a86	543
be6d306d	544	SET_ANALOG_MODE();
ce1d0a86 BL	545
	546	while (TRUE) {
	547	if (dosud) {
	548	dosud = FALSE;
	549	handle_setupdata();
	550	}
	551
	552	if (dosuspend) {
	553	dosuspend = FALSE;
	554	do {
	555	/* Make sure ext wakeups are cleared. */
3968bbfb	556	WAKEUPCS \|= bmWU \| bmWU2;
ce1d0a86 BL	557	SUSPEND = 1;
	558	PCON \|= 1;
	559	__asm
	560	nop
	561	nop
	562	nop
	563	nop
	564	nop
	565	nop
	566	nop
	567	__endasm;
	568	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	569
	570	/* Resume (TRM 6.4). */
	571	if (REMOTE_WAKEUP()) {
	572	delay(5);
	573	USBCS \|= bmSIGRESUME;
	574	delay(15);
	575	USBCS &= ~bmSIGRESUME;
	576	}
	577	}
	578	}
	579	}