[sigrok-firmware-fx2lafw.git] / sainsmart_dds120.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
	IOE = IOE^0x04;
	TF2 = 0;
}

/**
 * The gain stage is 2 stage approach. -6dB and -20dB on the first stage
 * (attentuator). The second stage is then doing the gain by 3 different
 * resistor values switched into the feedback loop.
 *
 * #Channel 0:
 * PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
 * PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
 * PC1=1; PC2=1; PC3= 0 -> Gain x0.4 =  -8dB
 * PC1=0; PC2=0; PC3= 0 -> Gain x0.5 =  -6dB
 * PC1=0; PC2=0; PC3= 1 -> Gain x1   =   0dB
 * PC1=0; PC2=1; PC3= 0 -> Gain x2   =  +6dB
 *
 * #Channel 1:
 * PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB 
 * PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
 * PE1=1; PC4=1; PC5= 0 -> Gain x0.4 =  -8dB
 * PE1=0; PC4=0; PC5= 0 -> Gain x0.5 =  -6dB
 * PE1=0; PC4=0; PC5= 1 -> Gain x1   =   0dB
 * PE1=0; PC4=1; PC5= 0 -> Gain x2   =  +6dB
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits_C, bit_E, mask_C, mask_E;

	if (channel == 0) {
		mask_C = 0x0E;
		mask_E = 0x00;
		bit_E = 0;
		switch (val) {
		case 1:
			bits_C = 0x02;
			break;
		case 2:
			bits_C = 0x06;
			break;
		case 5:
			bits_C = 0x00;
			break;
		case 10:
			bits_C = 0x04;
			break;
		case 20:
			bits_C = 0x08;
			break;
		default:
			return FALSE;
		}
	} else if (channel == 1) {
		mask_C = 0x30;
		mask_E = 0x02;
		switch (val) {
		case 1:
			bits_C = 0x00;
			bit_E = 0x02; 
			break;
		case 2:
			bits_C = 0x10;
			bit_E = 0x02; 
			break;
		case 5:
			bits_C = 0x00;
			bit_E = 0x00; 
			break;
		case 10:
			bits_C = 0x10;
			bit_E = 0x00; 
			break;
		case 20:
			bits_C = 0x20;
			bit_E = 0x00; 
			break;
		default:
			return FALSE;
		}
	} else {
		return FALSE;
	}
	IOC = (IOC & ~mask_C) | (bits_C & mask_C);
	IOE = (IOE & ~mask_E) | (bit_E & mask_E);
		
	return TRUE;
}

/**
 * Each LSB in the nibble of the byte controls the coupling per channel.
 *
 * Setting PE3 disables AC coupling capacitor on CH0.
 * Setting PE0 disables AC coupling capacitor on CH1.
 */
static void set_coupling(BYTE coupling_cfg)
{
	if (coupling_cfg & 0x01)
		IOE |= 0x08;
	else
		IOE &= ~0x08;

	if (coupling_cfg & 0x10)
		IOE |= 0x01;
	else
		IOE &= ~0x01;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, 0x40, 0xea },
	{ 16,    1,   1, 2, 0, 0x40, 0xea },
	{ 15,    1,   0, 2, 1, 0x40, 0xaa },
	{ 12,    2,   1, 2, 0, 0x40, 0xea },
	{ 11,    1,   1, 2, 0, 0x40, 0xaa },
	{  8,    3,   2, 2, 0, 0x40, 0xea },
	{  6,    2,   2, 2, 0, 0x40, 0xaa },
	{  5,    3,   2, 2, 0, 0x40, 0xaa },
	{  4,    6,   5, 2, 0, 0x40, 0xea },
	{  3,    5,   4, 2, 0, 0x40, 0xaa },
	{  2,   12,  11, 2, 0, 0x40, 0xea },
	{  1,   24,  23, 2, 0, 0x40, 0xea },
	{ 50,   48,  47, 2, 0, 0x40, 0xea },
	{ 20,  120, 119, 2, 0, 0x40, 0xea },
	{ 10,  240, 239, 2, 0, 0x40, 0xea },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTLx=0, FIFO
	 * wait 23, CTLx=1
	 * jump 0, CTLx=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTLx=0, FIFO
	 * jump 0, CTLx=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTLx=Z, FIFO, LOOP
	 *
	 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

static BOOL set_calibration_pulse(BYTE fs)
{
	switch (fs) {
	case 0:		// 100Hz
		RCAP2L = -10000 & 0xff;
		RCAP2H = (-10000 & 0xff00) >> 8;
		return TRUE;
	case 1:		// 1kHz
		RCAP2L = -1000 & 0xff;
		RCAP2H = (-1000 & 0xff00) >> 8;
		return TRUE;
	case 10:	// 1kHz
		RCAP2L = (BYTE)(-100 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	case 50:	// 50kHz
		RCAP2L = (BYTE)(-20 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	default:
		return FALSE;
	}
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe6) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	case 0xe5:
		set_coupling(EP0BUF[0]);
		return TRUE;
	case 0xe6:
		set_calibration_pulse(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -1000 & 0xff;
	RCAP2H = (-1000 & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE_UNCOND();

	PORTCCFG = 0;
	PORTACFG = 0;
	PORTECFG = 0;
	OEE = 0xFF;
	OEC = 0xff;
	OEA = 0x80;

	PA7 = 1;

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU | bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
ce1d0a86 BL	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
040a6eae	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
ce1d0a86 BL	19	*/
	20
	21	#include <fx2macros.h>
	22	#include <fx2ints.h>
	23	#include <autovector.h>
	24	#include <delay.h>
	25	#include <setupdat.h>
	26
	27	/* Change to support as many interfaces as you need. */
	28	static BYTE altiface = 0;
	29
	30	static volatile __bit dosud = FALSE;
	31	static volatile __bit dosuspend = FALSE;
	32
	33	extern __code BYTE highspd_dscr;
	34	extern __code BYTE fullspd_dscr;
	35
	36	void resume_isr(void) __interrupt RESUME_ISR
	37	{
	38	CLEAR_RESUME();
	39	}
	40
	41	void sudav_isr(void) __interrupt SUDAV_ISR
	42	{
	43	dosud = TRUE;
	44	CLEAR_SUDAV();
	45	}
	46
	47	void usbreset_isr(void) __interrupt USBRESET_ISR
	48	{
	49	handle_hispeed(FALSE);
	50	CLEAR_USBRESET();
	51	}
	52
	53	void hispeed_isr(void) __interrupt HISPEED_ISR
	54	{
	55	handle_hispeed(TRUE);
	56	CLEAR_HISPEED();
	57	}
	58
	59	void suspend_isr(void) __interrupt SUSPEND_ISR
	60	{
	61	dosuspend = TRUE;
	62	CLEAR_SUSPEND();
	63	}
	64
	65	void timer2_isr(void) __interrupt TF2_ISR
	66	{
3968bbfb	67	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
ce1d0a86 BL	68	IOE = IOE^0x04;
	69	TF2 = 0;
	70	}
	71
	72	/**
3968bbfb UH	73	* The gain stage is 2 stage approach. -6dB and -20dB on the first stage
	74	* (attentuator). The second stage is then doing the gain by 3 different
	75	* resistor values switched into the feedback loop.
	76	*
ce1d0a86 BL	77	* #Channel 0:
	78	* PC1=1; PC2=0; PC3= 0 -> Gain x0.1 = -20dB
	79	* PC1=1; PC2=0; PC3= 1 -> Gain x0.2 = -14dB
	80	* PC1=1; PC2=1; PC3= 0 -> Gain x0.4 = -8dB
	81	* PC1=0; PC2=0; PC3= 0 -> Gain x0.5 = -6dB
	82	* PC1=0; PC2=0; PC3= 1 -> Gain x1 = 0dB
	83	* PC1=0; PC2=1; PC3= 0 -> Gain x2 = +6dB
3968bbfb	84	*
ce1d0a86 BL	85	* #Channel 1:
	86	* PE1=1; PC4=0; PC5= 0 -> Gain x0.1 = -20dB
	87	* PE1=1; PC4=0; PC5= 1 -> Gain x0.2 = -14dB
	88	* PE1=1; PC4=1; PC5= 0 -> Gain x0.4 = -8dB
	89	* PE1=0; PC4=0; PC5= 0 -> Gain x0.5 = -6dB
	90	* PE1=0; PC4=0; PC5= 1 -> Gain x1 = 0dB
	91	* PE1=0; PC4=1; PC5= 0 -> Gain x2 = +6dB
	92	*/
	93	static BOOL set_voltage(BYTE channel, BYTE val)
	94	{
	95	BYTE bits_C, bit_E, mask_C, mask_E;
	96
	97	if (channel == 0) {
	98	mask_C = 0x0E;
	99	mask_E = 0x00;
	100	bit_E = 0;
	101	switch (val) {
	102	case 1:
	103	bits_C = 0x02;
	104	break;
	105	case 2:
	106	bits_C = 0x06;
	107	break;
	108	case 5:
	109	bits_C = 0x00;
	110	break;
	111	case 10:
	112	bits_C = 0x04;
	113	break;
	114	case 20:
	115	bits_C = 0x08;
	116	break;
	117	default:
	118	return FALSE;
	119	}
	120	} else if (channel == 1) {
	121	mask_C = 0x30;
	122	mask_E = 0x02;
	123	switch (val) {
	124	case 1:
	125	bits_C = 0x00;
	126	bit_E = 0x02;
	127	break;
	128	case 2:
	129	bits_C = 0x10;
	130	bit_E = 0x02;
	131	break;
	132	case 5:
	133	bits_C = 0x00;
	134	bit_E = 0x00;
	135	break;
	136	case 10:
	137	bits_C = 0x10;
	138	bit_E = 0x00;
	139	break;
	140	case 20:
	141	bits_C = 0x20;
	142	bit_E = 0x00;
	143	break;
	144	default:
	145	return FALSE;
	146	}
	147	} else {
	148	return FALSE;
149	}
150	IOC = (IOC & ~mask_C) \| (bits_C & mask_C);
151	IOE = (IOE & ~mask_E) \| (bit_E & mask_E);
152
153	return TRUE;
154	}
155
75ad0fa5 BL	156	/**
	157	* Each LSB in the nibble of the byte controls the coupling per channel.
	158	*
	159	* Setting PE3 disables AC coupling capacitor on CH0.
	160	* Setting PE0 disables AC coupling capacitor on CH1.
	161	*/
	162	static void set_coupling(BYTE coupling_cfg)
	163	{
	164	if (coupling_cfg & 0x01)
	165	IOE \|= 0x08;
	166	else
	167	IOE &= ~0x08;
	168
	169	if (coupling_cfg & 0x10)
	170	IOE \|= 0x01;
	171	else
	172	IOE &= ~0x01;
	173	}
	174
ce1d0a86 BL	175	static BOOL set_numchannels(BYTE numchannels)
	176	{
	177	if (numchannels == 1 \|\| numchannels == 2) {
	178	BYTE fifocfg = 7 + numchannels;
	179	EP2FIFOCFG = fifocfg;
	180	EP6FIFOCFG = fifocfg;
	181	return TRUE;
	182	}
	183
	184	return FALSE;
	185	}
	186
	187	static void clear_fifo(void)
	188	{
	189	GPIFABORT = 0xff;
	190	SYNCDELAY3;
	191	FIFORESET = 0x80;
	192	SYNCDELAY3;
	193	FIFORESET = 0x82;
	194	SYNCDELAY3;
	195	FIFORESET = 0x86;
	196	SYNCDELAY3;
	197	FIFORESET = 0;
	198	}
	199
	200	static void stop_sampling(void)
	201	{
	202	GPIFABORT = 0xff;
	203	SYNCDELAY3;
	204	INPKTEND = (altiface == 0) ? 6 : 2;
	205	}
	206
	207	static void start_sampling(void)
	208	{
	209	int i;
	210
	211	clear_fifo();
	212
	213	for (i = 0; i < 1000; i++);
	214
	215	while (!(GPIFTRIG & 0x80))
	216	;
	217
	218	SYNCDELAY3;
	219	GPIFTCB1 = 0x28;
	220	SYNCDELAY3;
	221	GPIFTCB0 = 0;
	222	GPIFTRIG = (altiface == 0) ? 6 : 4;
	223
	224	}
	225
	226	static void select_interface(BYTE alt)
	227	{
	228	const BYTE *pPacketSize = \
	229	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
	230	+ (9 + (16 * alt) + 9 + 4);
	231
	232	altiface = alt;
	233
	234	if (alt == 0) {
	235	/* Bulk on EP6. */
	236	EP2CFG = 0x00;
	237	EP6CFG = 0xe0;
	238	EP6GPIFFLGSEL = 1;
239	EP6AUTOINLENL = pPacketSize[0];
240	EP6AUTOINLENH = pPacketSize[1];
241	} else {
242	/* Iso on EP2. */
243	EP2CFG = 0xd8;
244	EP6CFG = 0x00;
245	EP2GPIFFLGSEL = 1;
246	EP2AUTOINLENL = pPacketSize[0];
247	EP2AUTOINLENH = pPacketSize[1] & 0x7;
248	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
249	}
250	}
251
252	static const struct samplerate_info {
253	BYTE rate;
254	BYTE wait0;
255	BYTE wait1;
256	BYTE opc0;
257	BYTE opc1;
258	BYTE out0;
259	BYTE ifcfg;
260	} samplerates[] = {
261	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
262	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
263	{ 24, 1, 0, 2, 1, 0x40, 0xea },
264	{ 16, 1, 1, 2, 0, 0x40, 0xea },
33c275bb	265	{ 15, 1, 0, 2, 1, 0x40, 0xaa },
ce1d0a86	266	{ 12, 2, 1, 2, 0, 0x40, 0xea },
33c275bb	267	{ 11, 1, 1, 2, 0, 0x40, 0xaa },
ce1d0a86	268	{ 8, 3, 2, 2, 0, 0x40, 0xea },
33c275bb BL	269	{ 6, 2, 2, 2, 0, 0x40, 0xaa },
33c275bb BL	270	{ 5, 3, 2, 2, 0, 0x40, 0xaa },
ce1d0a86	271	{ 4, 6, 5, 2, 0, 0x40, 0xea },
33c275bb	272	{ 3, 5, 4, 2, 0, 0x40, 0xaa },
ce1d0a86 BL	273	{ 2, 12, 11, 2, 0, 0x40, 0xea },
	274	{ 1, 24, 23, 2, 0, 0x40, 0xea },
	275	{ 50, 48, 47, 2, 0, 0x40, 0xea },
	276	{ 20, 120, 119, 2, 0, 0x40, 0xea },
	277	{ 10, 240, 239, 2, 0, 0x40, 0xea },
	278	};
	279
	280	static BOOL set_samplerate(BYTE rate)
	281	{
	282	BYTE i = 0;
	283
	284	while (samplerates[i].rate != rate) {
	285	i++;
	286	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	287	return FALSE;
	288	}
	289
	290	IFCONFIG = samplerates[i].ifcfg;
	291
	292	AUTOPTRSETUP = 7;
24373950	293	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
ce1d0a86 BL	294	AUTOPTRL2 = 0x00;
	295
	296	/*
	297	* The program for low-speed, e.g. 1 MHz, is:
3968bbfb UH	298	* wait 24, CTLx=0, FIFO
	299	* wait 23, CTLx=1
	300	* jump 0, CTLx=1
ce1d0a86 BL	301	*
ce1d0a86 BL	302	* The program for 24 MHz is:
3968bbfb UH	303	* wait 1, CTLx=0, FIFO
3968bbfb UH	304	* jump 0, CTLx=1
ce1d0a86 BL	305	*
ce1d0a86 BL	306	* The program for 30/48 MHz is:
3968bbfb UH	307	* jump 0, CTLx=Z, FIFO, LOOP
	308	*
	309	* (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
ce1d0a86 BL	310	*/
ce1d0a86 BL	311
24373950	312	/* LENGTH / BRANCH 0-7 */
ce1d0a86 BL	313	EXTAUTODAT2 = samplerates[i].wait0;
	314	EXTAUTODAT2 = samplerates[i].wait1;
	315	EXTAUTODAT2 = 1;
	316	EXTAUTODAT2 = 0;
	317	EXTAUTODAT2 = 0;
	318	EXTAUTODAT2 = 0;
	319	EXTAUTODAT2 = 0;
	320	EXTAUTODAT2 = 0;
	321
24373950	322	/* OPCODE 0-7 */
ce1d0a86 BL	323	EXTAUTODAT2 = samplerates[i].opc0;
ce1d0a86 BL	324	EXTAUTODAT2 = samplerates[i].opc1;
24373950	325	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
ce1d0a86 BL	326	EXTAUTODAT2 = 0;
	327	EXTAUTODAT2 = 0;
	328	EXTAUTODAT2 = 0;
	329	EXTAUTODAT2 = 0;
	330	EXTAUTODAT2 = 0;
	331
24373950	332	/* OUTPUT 0-7 */
ce1d0a86	333	EXTAUTODAT2 = samplerates[i].out0;
3968bbfb UH	334	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
3968bbfb UH	335	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
24373950 UH	336	EXTAUTODAT2 = 0;
	337	EXTAUTODAT2 = 0;
	338	EXTAUTODAT2 = 0;
	339	EXTAUTODAT2 = 0;
	340	EXTAUTODAT2 = 0;
ce1d0a86	341
24373950	342	/* LOGIC FUNCTION 0-7 */
ce1d0a86 BL	343	EXTAUTODAT2 = 0;
	344	EXTAUTODAT2 = 0;
	345	EXTAUTODAT2 = 0;
	346	EXTAUTODAT2 = 0;
	347	EXTAUTODAT2 = 0;
	348	EXTAUTODAT2 = 0;
	349	EXTAUTODAT2 = 0;
	350	EXTAUTODAT2 = 0;
	351
	352	for (i = 0; i < 96; i++)
	353	EXTAUTODAT2 = 0;
	354
	355	return TRUE;
	356	}
	357
a425fae9 BL	358	static BOOL set_calibration_pulse(BYTE fs)
	359	{
	360	switch (fs) {
	361	case 0: // 100Hz
	362	RCAP2L = -10000 & 0xff;
386296a7	363	RCAP2H = (-10000 & 0xff00) >> 8;
a425fae9 BL	364	return TRUE;
	365	case 1: // 1kHz
	366	RCAP2L = -1000 & 0xff;
386296a7	367	RCAP2H = (-1000 & 0xff00) >> 8;
a425fae9 BL	368	return TRUE;
a425fae9 BL	369	case 10: // 1kHz
386296a7	370	RCAP2L = (BYTE)(-100 & 0xff);
a425fae9 BL	371	RCAP2H = 0xff;
	372	return TRUE;
	373	case 50: // 50kHz
386296a7	374	RCAP2L = (BYTE)(-20 & 0xff);
a425fae9 BL	375	RCAP2H = 0xff;
	376	return TRUE;
	377	default:
	378	return FALSE;
	379	}
	380	}
	381
ce1d0a86 BL	382	/* Set alt_ifc to the current alt interface for ifc. /
	383	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	384	{
	385	(void)ifc;
	386
	387	*alt_ifc = altiface;
	388
	389	return TRUE;
	390	}
	391
	392	/*
	393	* Return TRUE if you set the interface requested.
	394	*
	395	* Note: This function should reconfigure and reset the endpoints
	396	* according to the interface descriptors you provided.
	397	*/
	398	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	399	{
	400	if (ifc == 0)
	401	select_interface(alt_ifc);
	402
	403	return TRUE;
	404	}
	405
	406	BYTE handle_get_configuration(void)
	407	{
	408	/* We only support configuration 0. */
	409	return 0;
	410	}
	411
	412	BOOL handle_set_configuration(BYTE cfg)
	413	{
	414	/* We only support configuration 0. */
	415	(void)cfg;
	416
	417	return TRUE;
	418	}
	419
	420	BOOL handle_vendorcommand(BYTE cmd)
	421	{
	422	stop_sampling();
	423
	424	/* Clear EP0BCH/L for each valid command. */
a425fae9	425	if (cmd >= 0xe0 && cmd <= 0xe6) {
ce1d0a86 BL	426	EP0BCH = 0;
	427	EP0BCL = 0;
	428	while (EP0CS & bmEPBUSY);
	429	}
	430
	431	switch (cmd) {
	432	case 0xe0:
	433	case 0xe1:
	434	set_voltage(cmd - 0xe0, EP0BUF[0]);
	435	return TRUE;
	436	case 0xe2:
	437	set_samplerate(EP0BUF[0]);
	438	return TRUE;
	439	case 0xe3:
	440	if (EP0BUF[0] == 1)
	441	start_sampling();
	442	return TRUE;
	443	case 0xe4:
	444	set_numchannels(EP0BUF[0]);
	445	return TRUE;
75ad0fa5 BL	446	case 0xe5:
	447	set_coupling(EP0BUF[0]);
	448	return TRUE;
a425fae9 BL	449	case 0xe6:
	450	set_calibration_pulse(EP0BUF[0]);
	451	return TRUE;
ce1d0a86 BL	452	}
	453
	454	return FALSE; /* Not handled by handlers. */
	455	}
	456
	457	static void init(void)
	458	{
	459	EP4CFG = 0;
	460	EP8CFG = 0;
	461
	462	/* In idle mode tristate all outputs. */
24373950 UH	463	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
24373950 UH	464	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
ce1d0a86 BL	465	GPIFWFSELECT = 0x00;
	466	GPIFREADYSTAT = 0x00;
	467
	468	stop_sampling();
	469
	470	set_voltage(0, 1);
	471	set_voltage(1, 1);
	472	set_samplerate(1);
	473	set_numchannels(2);
	474	select_interface(0);
	475	}
	476
	477	static void main(void)
	478	{
	479	/* Save energy. */
	480	SETCPUFREQ(CLK_12M);
	481
	482	init();
	483
	484	/* Set up interrupts. */
	485	USE_USB_INTS();
	486
	487	ENABLE_SUDAV();
	488	ENABLE_USBRESET();
	489	ENABLE_HISPEED();
	490	ENABLE_SUSPEND();
	491	ENABLE_RESUME();
	492
	493	/* Global (8051) interrupt enable. */
	494	EA = 1;
	495
	496	/* Init timer2. */
	497	RCAP2L = -1000 & 0xff;
386296a7	498	RCAP2H = (-1000 & 0xff00) >> 8;
ce1d0a86 BL	499	T2CON = 0;
	500	ET2 = 1;
	501	TR2 = 1;
	502
	503	RENUMERATE_UNCOND();
	504
	505	PORTCCFG = 0;
	506	PORTACFG = 0;
	507	PORTECFG = 0;
	508	OEE = 0xFF;
	509	OEC = 0xff;
	510	OEA = 0x80;
	511
	512	PA7 = 1;
	513
	514	while (TRUE) {
	515	if (dosud) {
	516	dosud = FALSE;
	517	handle_setupdata();
	518	}
	519
	520	if (dosuspend) {
	521	dosuspend = FALSE;
	522	do {
	523	/* Make sure ext wakeups are cleared. */
3968bbfb	524	WAKEUPCS \|= bmWU \| bmWU2;
ce1d0a86 BL	525	SUSPEND = 1;
	526	PCON \|= 1;
	527	__asm
	528	nop
	529	nop
	530	nop
	531	nop
	532	nop
	533	nop
	534	nop
	535	__endasm;
	536	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	537
	538	/* Resume (TRM 6.4). */
	539	if (REMOTE_WAKEUP()) {
	540	delay(5);
	541	USBCS \|= bmSIGRESUME;
	542	delay(15);
	543	USBCS &= ~bmSIGRESUME;
	544	}
	545	}
	546	}
	547	}