[sigrok-firmware-fx2lafw.git] / hantek_6022be.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile WORD ledcounter = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	PA7 = !PA7;
	if (ledcounter) {
		if (--ledcounter == 0) {
			/* Clear LED. */
			PC0 = 1;
			PC1 = 1;
		}
	}
	TF2 = 0;
}

/*
 * This sets three bits for each channel, one channel at a time.
 * For channel 0 we want to set bits 5, 6 & 7
 * For channel 1 we want to set bits 2, 3 & 4
 *
 * We convert the input values that are strange due to original
 * firmware code into the value of the three bits as follows:
 *
 * val -> bits
 * 1  -> 010b
 * 2  -> 001b
 * 5  -> 000b
 * 10 -> 011b
 *
 * The third bit is always zero since there are only four outputs connected
 * in the serial selector chip.
 *
 * The multiplication of the converted value by 0x24 sets the relevant bits in
 * both channels and then we mask it out to only affect the channel currently
 * requested.
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits, mask;

	switch (val) {
	case 1:
		bits = 0x24 * 2;
		break;
	case 2:
		bits = 0x24 * 1;
		break;
	case 5:
		bits = 0x24 * 0;
		break;
	case 10:
		bits = 0x24 * 3;
		break;
	default:
		return FALSE;
	}

	mask = (channel) ? 0xe0 : 0x1c;
	IOC = (IOC & ~mask) | (bits & mask);

	return TRUE;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

	/* Set green LED, don't clear LED. */
	ledcounter = 0;
	PC0 = 1;
	PC1 = 0;
}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, 0x40, 0xca },
	{ 16,    1,   1, 2, 0, 0x40, 0xca },
	{ 12,    2,   1, 2, 0, 0x40, 0xca },
	{  8,    3,   2, 2, 0, 0x40, 0xca },
	{  4,    6,   5, 2, 0, 0x40, 0xca },
	{  2,   12,  11, 2, 0, 0x40, 0xca },
	{  1,   24,  23, 2, 0, 0x40, 0xca },
	{ 50,   48,  47, 2, 0, 0x40, 0xca },
	{ 20,  120, 119, 2, 0, 0x40, 0xca },
	{ 10,  240, 239, 2, 0, 0x40, 0xca },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTL2=0, FIFO
	 * wait 23, CTL2=1
	 * jump 0, CTL2=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTL2=0, FIFO
	 * jump 0, CTL2=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTL2=Z, FIFO, LOOP
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = 0x44; /* OE0=1, CTL0=1 */
	EXTAUTODAT2 = 0x44; /* OE0=1, CTL0=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Set red LED. */
	PC0 = 0;
	PC1 = 1;
	ledcounter = 1000;

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe4) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -500 & 0xff;
	RCAP2H = (-500 & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE();

	PORTCCFG = 0;
	PORTACFG = 0;
	OEC = 0xff;
	OEA = 0x80;

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU|bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
484b3aa0 UH	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
189db3d4 UH	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
484b3aa0	20	*/
189db3d4 UH	21
	22	#include <fx2macros.h>
	23	#include <fx2ints.h>
	24	#include <autovector.h>
	25	#include <delay.h>
	26	#include <setupdat.h>
	27
cc789c14	28	/* Change to support as many interfaces as you need. */
0ab4ea5d	29	static BYTE altiface = 0;
189db3d4	30
0ab4ea5d	31	static volatile WORD ledcounter = 0;
189db3d4	32
0ab4ea5d UH	33	static volatile __bit dosud = FALSE;
0ab4ea5d UH	34	static volatile __bit dosuspend = FALSE;
cc789c14 UH	35
	36	extern __code BYTE highspd_dscr;
	37	extern __code BYTE fullspd_dscr;
189db3d4	38
cc789c14 UH	39	void resume_isr(void) __interrupt RESUME_ISR
	40	{
	41	CLEAR_RESUME();
189db3d4	42	}
cc789c14 UH	43
	44	void sudav_isr(void) __interrupt SUDAV_ISR
	45	{
	46	dosud = TRUE;
	47	CLEAR_SUDAV();
189db3d4	48	}
cc789c14 UH	49
	50	void usbreset_isr(void) __interrupt USBRESET_ISR
	51	{
	52	handle_hispeed(FALSE);
	53	CLEAR_USBRESET();
189db3d4	54	}
cc789c14 UH	55
	56	void hispeed_isr(void) __interrupt HISPEED_ISR
	57	{
	58	handle_hispeed(TRUE);
	59	CLEAR_HISPEED();
189db3d4 UH	60	}
189db3d4 UH	61
cc789c14 UH	62	void suspend_isr(void) __interrupt SUSPEND_ISR
	63	{
	64	dosuspend = TRUE;
	65	CLEAR_SUSPEND();
189db3d4 UH	66	}
189db3d4 UH	67
cc789c14 UH	68	void timer2_isr(void) __interrupt TF2_ISR
	69	{
	70	PA7 = !PA7;
	71	if (ledcounter) {
	72	if (--ledcounter == 0) {
	73	/* Clear LED. */
	74	PC0 = 1;
	75	PC1 = 1;
	76	}
	77	}
	78	TF2 = 0;
189db3d4	79	}
189db3d4	80
cc789c14 UH	81	/*
cc789c14 UH	82	* This sets three bits for each channel, one channel at a time.
189db3d4 UH	83	* For channel 0 we want to set bits 5, 6 & 7
	84	* For channel 1 we want to set bits 2, 3 & 4
	85	*
cc789c14 UH	86	* We convert the input values that are strange due to original
	87	* firmware code into the value of the three bits as follows:
	88	*
189db3d4 UH	89	* val -> bits
	90	* 1 -> 010b
	91	* 2 -> 001b
	92	* 5 -> 000b
	93	* 10 -> 011b
	94	*
cc789c14 UH	95	* The third bit is always zero since there are only four outputs connected
cc789c14 UH	96	* in the serial selector chip.
189db3d4 UH	97	*
	98	* The multiplication of the converted value by 0x24 sets the relevant bits in
	99	* both channels and then we mask it out to only affect the channel currently
	100	* requested.
	101	*/
0ab4ea5d	102	static BOOL set_voltage(BYTE channel, BYTE val)
189db3d4	103	{
cc789c14 UH	104	BYTE bits, mask;
	105
	106	switch (val) {
	107	case 1:
	108	bits = 0x24 * 2;
	109	break;
	110	case 2:
	111	bits = 0x24 * 1;
	112	break;
	113	case 5:
	114	bits = 0x24 * 0;
	115	break;
	116	case 10:
	117	bits = 0x24 * 3;
	118	break;
	119	default:
	120	return FALSE;
	121	}
	122
	123	mask = (channel) ? 0xe0 : 0x1c;
	124	IOC = (IOC & ~mask) \| (bits & mask);
189db3d4	125
cc789c14	126	return TRUE;
189db3d4 UH	127	}
189db3d4 UH	128
0ab4ea5d	129	static BOOL set_numchannels(BYTE numchannels)
189db3d4	130	{
cc789c14 UH	131	if (numchannels == 1 \|\| numchannels == 2) {
	132	BYTE fifocfg = 7 + numchannels;
	133	EP2FIFOCFG = fifocfg;
	134	EP6FIFOCFG = fifocfg;
	135	return TRUE;
	136	}
	137
	138	return FALSE;
189db3d4 UH	139	}
189db3d4 UH	140
0ab4ea5d	141	static void clear_fifo(void)
189db3d4	142	{
cc789c14 UH	143	GPIFABORT = 0xff;
	144	SYNCDELAY3;
	145	FIFORESET = 0x80;
	146	SYNCDELAY3;
	147	FIFORESET = 0x82;
	148	SYNCDELAY3;
	149	FIFORESET = 0x86;
	150	SYNCDELAY3;
	151	FIFORESET = 0;
189db3d4 UH	152	}
189db3d4 UH	153
0ab4ea5d	154	static void stop_sampling(void)
189db3d4	155	{
cc789c14 UH	156	GPIFABORT = 0xff;
	157	SYNCDELAY3;
	158	INPKTEND = (altiface == 0) ? 6 : 2;
189db3d4 UH	159	}
189db3d4 UH	160
0ab4ea5d	161	static void start_sampling(void)
189db3d4	162	{
cc789c14 UH	163	int i;
	164
	165	clear_fifo();
	166
	167	for (i = 0; i < 1000; i++);
	168
	169	while (!(GPIFTRIG & 0x80))
	170	;
	171
	172	SYNCDELAY3;
	173	GPIFTCB1 = 0x28;
	174	SYNCDELAY3;
	175	GPIFTCB0 = 0;
	176	GPIFTRIG = (altiface == 0) ? 6 : 4;
	177
	178	/* Set green LED, don't clear LED. */
	179	ledcounter = 0;
	180	PC0 = 1;
	181	PC1 = 0;
189db3d4 UH	182	}
189db3d4 UH	183
0ab4ea5d	184	static void select_interface(BYTE alt)
189db3d4	185	{
cc789c14	186	const BYTE *pPacketSize = \
374453b9	187	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
cc789c14 UH	188	+ (9 + (16 * alt) + 9 + 4);
	189
	190	altiface = alt;
	191
	192	if (alt == 0) {
	193	/* Bulk on EP6. */
	194	EP2CFG = 0x00;
	195	EP6CFG = 0xe0;
	196	EP6GPIFFLGSEL = 1;
	197	EP6AUTOINLENL = pPacketSize[0];
	198	EP6AUTOINLENH = pPacketSize[1];
	199	} else {
	200	/* Iso on EP2. */
	201	EP2CFG = 0xd8;
	202	EP6CFG = 0x00;
	203	EP2GPIFFLGSEL = 1;
	204	EP2AUTOINLENL = pPacketSize[0];
	205	EP2AUTOINLENH = pPacketSize[1] & 0x7;
	206	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	207	}
189db3d4 UH	208	}
189db3d4 UH	209
0ab4ea5d	210	static const struct samplerate_info {
cc789c14 UH	211	BYTE rate;
	212	BYTE wait0;
	213	BYTE wait1;
	214	BYTE opc0;
	215	BYTE opc1;
	216	BYTE out0;
	217	BYTE ifcfg;
189db3d4	218	} samplerates[] = {
374453b9 UH	219	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
	220	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
	221	{ 24, 1, 0, 2, 1, 0x40, 0xca },
	222	{ 16, 1, 1, 2, 0, 0x40, 0xca },
	223	{ 12, 2, 1, 2, 0, 0x40, 0xca },
	224	{ 8, 3, 2, 2, 0, 0x40, 0xca },
	225	{ 4, 6, 5, 2, 0, 0x40, 0xca },
	226	{ 2, 12, 11, 2, 0, 0x40, 0xca },
	227	{ 1, 24, 23, 2, 0, 0x40, 0xca },
	228	{ 50, 48, 47, 2, 0, 0x40, 0xca },
	229	{ 20, 120, 119, 2, 0, 0x40, 0xca },
	230	{ 10, 240, 239, 2, 0, 0x40, 0xca },
189db3d4 UH	231	};
189db3d4 UH	232
0ab4ea5d	233	static BOOL set_samplerate(BYTE rate)
189db3d4	234	{
cc789c14 UH	235	BYTE i = 0;
	236
	237	while (samplerates[i].rate != rate) {
	238	i++;
	239	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	240	return FALSE;
	241	}
	242
	243	IFCONFIG = samplerates[i].ifcfg;
	244
	245	AUTOPTRSETUP = 7;
24373950	246	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
cc789c14 UH	247	AUTOPTRL2 = 0x00;
	248
	249	/*
	250	* The program for low-speed, e.g. 1 MHz, is:
	251	* wait 24, CTL2=0, FIFO
	252	* wait 23, CTL2=1
	253	* jump 0, CTL2=1
	254	*
	255	* The program for 24 MHz is:
	256	* wait 1, CTL2=0, FIFO
	257	* jump 0, CTL2=1
	258	*
	259	* The program for 30/48 MHz is:
	260	* jump 0, CTL2=Z, FIFO, LOOP
	261	*/
	262
24373950	263	/* LENGTH / BRANCH 0-7 */
cc789c14 UH	264	EXTAUTODAT2 = samplerates[i].wait0;
	265	EXTAUTODAT2 = samplerates[i].wait1;
	266	EXTAUTODAT2 = 1;
	267	EXTAUTODAT2 = 0;
	268	EXTAUTODAT2 = 0;
	269	EXTAUTODAT2 = 0;
	270	EXTAUTODAT2 = 0;
189db3d4	271	EXTAUTODAT2 = 0;
189db3d4	272
24373950	273	/* OPCODE 0-7 */
cc789c14 UH	274	EXTAUTODAT2 = samplerates[i].opc0;
cc789c14 UH	275	EXTAUTODAT2 = samplerates[i].opc1;
24373950	276	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
cc789c14 UH	277	EXTAUTODAT2 = 0;
	278	EXTAUTODAT2 = 0;
	279	EXTAUTODAT2 = 0;
	280	EXTAUTODAT2 = 0;
	281	EXTAUTODAT2 = 0;
	282
24373950	283	/* OUTPUT 0-7 */
cc789c14	284	EXTAUTODAT2 = samplerates[i].out0;
24373950 UH	285	EXTAUTODAT2 = 0x44; /* OE0=1, CTL0=1 */
	286	EXTAUTODAT2 = 0x44; /* OE0=1, CTL0=1 */
	287	EXTAUTODAT2 = 0;
	288	EXTAUTODAT2 = 0;
	289	EXTAUTODAT2 = 0;
	290	EXTAUTODAT2 = 0;
	291	EXTAUTODAT2 = 0;
cc789c14	292
24373950	293	/* LOGIC FUNCTION 0-7 */
cc789c14 UH	294	EXTAUTODAT2 = 0;
	295	EXTAUTODAT2 = 0;
	296	EXTAUTODAT2 = 0;
	297	EXTAUTODAT2 = 0;
	298	EXTAUTODAT2 = 0;
	299	EXTAUTODAT2 = 0;
	300	EXTAUTODAT2 = 0;
	301	EXTAUTODAT2 = 0;
	302
	303	for (i = 0; i < 96; i++)
	304	EXTAUTODAT2 = 0;
	305
	306	return TRUE;
189db3d4	307	}
cc789c14 UH	308
	309	/* Set alt_ifc to the current alt interface for ifc. /
	310	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	311	{
	312	(void)ifc;
	313
	314	*alt_ifc = altiface;
	315
	316	return TRUE;
189db3d4 UH	317	}
189db3d4 UH	318
cc789c14 UH	319	/*
	320	* Return TRUE if you set the interface requested.
	321	*
	322	* Note: This function should reconfigure and reset the endpoints
	323	* according to the interface descriptors you provided.
	324	*/
	325	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	326	{
	327	if (ifc == 0)
	328	select_interface(alt_ifc);
	329
	330	return TRUE;
189db3d4 UH	331	}
189db3d4 UH	332
cc789c14 UH	333	BYTE handle_get_configuration(void)
	334	{
	335	/* We only support configuration 0. */
	336	return 0;
189db3d4 UH	337	}
189db3d4 UH	338
cc789c14 UH	339	BOOL handle_set_configuration(BYTE cfg)
	340	{
	341	/* We only support configuration 0. */
	342	(void)cfg;
	343
189db3d4	344	return TRUE;
189db3d4 UH	345	}
189db3d4 UH	346
cc789c14 UH	347	BOOL handle_vendorcommand(BYTE cmd)
	348	{
	349	stop_sampling();
	350
	351	/* Set red LED. */
	352	PC0 = 0;
	353	PC1 = 1;
	354	ledcounter = 1000;
	355
38e32023 UH	356	/* Clear EP0BCH/L for each valid command. */
38e32023 UH	357	if (cmd >= 0xe0 && cmd <= 0xe4) {
cc789c14 UH	358	EP0BCH = 0;
	359	EP0BCL = 0;
	360	while (EP0CS & bmEPBUSY);
38e32023 UH	361	}
	362
	363	switch (cmd) {
	364	case 0xe0:
	365	case 0xe1:
cc789c14 UH	366	set_voltage(cmd - 0xe0, EP0BUF[0]);
	367	return TRUE;
	368	case 0xe2:
cc789c14 UH	369	set_samplerate(EP0BUF[0]);
	370	return TRUE;
	371	case 0xe3:
cc789c14 UH	372	if (EP0BUF[0] == 1)
	373	start_sampling();
	374	return TRUE;
	375	case 0xe4:
cc789c14 UH	376	set_numchannels(EP0BUF[0]);
	377	return TRUE;
	378	}
	379
	380	return FALSE; /* Not handled by handlers. */
	381	}
	382
0ab4ea5d	383	static void init(void)
cc789c14 UH	384	{
	385	EP4CFG = 0;
	386	EP8CFG = 0;
	387
	388	/* In idle mode tristate all outputs. */
24373950 UH	389	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
24373950 UH	390	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
cc789c14 UH	391	GPIFWFSELECT = 0x00;
	392	GPIFREADYSTAT = 0x00;
	393
	394	stop_sampling();
	395
	396	set_voltage(0, 1);
	397	set_voltage(1, 1);
	398	set_samplerate(1);
	399	set_numchannels(2);
	400	select_interface(0);
189db3d4	401	}
fb4075d5	402
0ab4ea5d	403	static void main(void)
fb4075d5 UH	404	{
	405	/* Save energy. */
	406	SETCPUFREQ(CLK_12M);
	407
	408	init();
	409
	410	/* Set up interrupts. */
	411	USE_USB_INTS();
	412
	413	ENABLE_SUDAV();
	414	ENABLE_USBRESET();
	415	ENABLE_HISPEED();
	416	ENABLE_SUSPEND();
	417	ENABLE_RESUME();
	418
	419	/* Global (8051) interrupt enable. */
	420	EA = 1;
	421
	422	/* Init timer2. */
	423	RCAP2L = -500 & 0xff;
386296a7	424	RCAP2H = (-500 & 0xff00) >> 8;
fb4075d5 UH	425	T2CON = 0;
	426	ET2 = 1;
	427	TR2 = 1;
	428
	429	RENUMERATE();
	430
	431	PORTCCFG = 0;
	432	PORTACFG = 0;
	433	OEC = 0xff;
	434	OEA = 0x80;
	435
	436	while (TRUE) {
	437	if (dosud) {
	438	dosud = FALSE;
	439	handle_setupdata();
	440	}
	441
	442	if (dosuspend) {
	443	dosuspend = FALSE;
	444	do {
	445	/* Make sure ext wakeups are cleared. */
	446	WAKEUPCS \|= bmWU\|bmWU2;
	447	SUSPEND = 1;
	448	PCON \|= 1;
	449	__asm
	450	nop
	451	nop
	452	nop
	453	nop
	454	nop
	455	nop
	456	nop
	457	__endasm;
	458	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	459
	460	/* Resume (TRM 6.4). */
	461	if (REMOTE_WAKEUP()) {
	462	delay(5);
	463	USBCS \|= bmSIGRESUME;
	464	delay(15);
	465	USBCS &= ~bmSIGRESUME;
	466	}
	467	}
	468	}
	469	}