[sigrok-firmware-fx2lafw.git] / hantek_6022be.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

#define SET_ANALOG_MODE()

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile WORD ledcounter = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
	PA7 = !PA7;

	if (ledcounter) {
		if (--ledcounter == 0) {
			/* Clear LED. */
			PC0 = 1;
			PC1 = 1;
		}
	}

	TF2 = 0;
}

/*
 * This sets three bits for each channel, one channel at a time.
 * For channel 0 we want to set bits 5, 6 & 7
 * For channel 1 we want to set bits 2, 3 & 4
 *
 * We convert the input values that are strange due to original
 * firmware code into the value of the three bits as follows:
 *
 * val -> bits
 * 1  -> 010b
 * 2  -> 001b
 * 5  -> 000b
 * 10 -> 011b
 *
 * The third bit is always zero since there are only four outputs connected
 * in the serial selector chip.
 *
 * The multiplication of the converted value by 0x24 sets the relevant bits in
 * both channels and then we mask it out to only affect the channel currently
 * requested.
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits, mask;

	switch (val) {
	case 1:
		bits = 0x24 * 2;
		break;
	case 2:
		bits = 0x24 * 1;
		break;
	case 5:
		bits = 0x24 * 0;
		break;
	case 10:
		bits = 0x24 * 3;
		break;
	default:
		return FALSE;
	}

	mask = (channel) ? 0xe0 : 0x1c;
	IOC = (IOC & ~mask) | (bits & mask);

	return TRUE;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	SET_ANALOG_MODE();

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

	/* Set green LED, don't clear LED. */
	ledcounter = 0;
	PC0 = 1;
	PC1 = 0;
}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, 0x40, 0xca },
	{ 16,    1,   1, 2, 0, 0x40, 0xca },
	{ 12,    2,   1, 2, 0, 0x40, 0xca },
	{  8,    3,   2, 2, 0, 0x40, 0xca },
	{  4,    6,   5, 2, 0, 0x40, 0xca },
	{  2,   12,  11, 2, 0, 0x40, 0xca },
	{  1,   24,  23, 2, 0, 0x40, 0xca },
	{ 50,   48,  47, 2, 0, 0x40, 0xca },
	{ 20,  120, 119, 2, 0, 0x40, 0xca },
	{ 10,  240, 239, 2, 0, 0x40, 0xca },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTLx=0, FIFO
	 * wait 23, CTLx=1
	 * jump 0, CTLx=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTLx=0, FIFO
	 * jump 0, CTLx=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTLx=Z, FIFO, LOOP
	 *
	 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Set red LED. */
	PC0 = 0;
	PC1 = 1;
	ledcounter = 1000;

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe4) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	SET_ANALOG_MODE();

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -500 & 0xff;
	RCAP2H = (-500 & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE();

	PORTCCFG = 0;
	PORTACFG = 0;
	OEC = 0xff;
	OEA = 0x80;

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU | bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
484b3aa0 UH	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
189db3d4 UH	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
040a6eae	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
484b3aa0	19	*/
189db3d4 UH	20
	21	#include <fx2macros.h>
	22	#include <fx2ints.h>
	23	#include <autovector.h>
	24	#include <delay.h>
	25	#include <setupdat.h>
	26
be6d306d UH	27	#define SET_ANALOG_MODE()
be6d306d UH	28
cc789c14	29	/* Change to support as many interfaces as you need. */
0ab4ea5d	30	static BYTE altiface = 0;
189db3d4	31
0ab4ea5d	32	static volatile WORD ledcounter = 0;
189db3d4	33
0ab4ea5d UH	34	static volatile __bit dosud = FALSE;
0ab4ea5d UH	35	static volatile __bit dosuspend = FALSE;
cc789c14 UH	36
	37	extern __code BYTE highspd_dscr;
	38	extern __code BYTE fullspd_dscr;
189db3d4	39
cc789c14 UH	40	void resume_isr(void) __interrupt RESUME_ISR
	41	{
	42	CLEAR_RESUME();
189db3d4	43	}
cc789c14 UH	44
	45	void sudav_isr(void) __interrupt SUDAV_ISR
	46	{
	47	dosud = TRUE;
	48	CLEAR_SUDAV();
189db3d4	49	}
cc789c14 UH	50
	51	void usbreset_isr(void) __interrupt USBRESET_ISR
	52	{
	53	handle_hispeed(FALSE);
	54	CLEAR_USBRESET();
189db3d4	55	}
cc789c14 UH	56
	57	void hispeed_isr(void) __interrupt HISPEED_ISR
	58	{
	59	handle_hispeed(TRUE);
	60	CLEAR_HISPEED();
189db3d4 UH	61	}
189db3d4 UH	62
cc789c14 UH	63	void suspend_isr(void) __interrupt SUSPEND_ISR
	64	{
	65	dosuspend = TRUE;
	66	CLEAR_SUSPEND();
189db3d4 UH	67	}
189db3d4 UH	68
cc789c14 UH	69	void timer2_isr(void) __interrupt TF2_ISR
cc789c14 UH	70	{
3968bbfb	71	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
cc789c14	72	PA7 = !PA7;
3968bbfb	73
cc789c14 UH	74	if (ledcounter) {
	75	if (--ledcounter == 0) {
	76	/* Clear LED. */
	77	PC0 = 1;
	78	PC1 = 1;
	79	}
	80	}
3968bbfb	81
cc789c14	82	TF2 = 0;
189db3d4	83	}
189db3d4	84
cc789c14 UH	85	/*
cc789c14 UH	86	* This sets three bits for each channel, one channel at a time.
189db3d4 UH	87	* For channel 0 we want to set bits 5, 6 & 7
	88	* For channel 1 we want to set bits 2, 3 & 4
	89	*
cc789c14 UH	90	* We convert the input values that are strange due to original
	91	* firmware code into the value of the three bits as follows:
	92	*
189db3d4 UH	93	* val -> bits
	94	* 1 -> 010b
	95	* 2 -> 001b
	96	* 5 -> 000b
	97	* 10 -> 011b
	98	*
cc789c14 UH	99	* The third bit is always zero since there are only four outputs connected
cc789c14 UH	100	* in the serial selector chip.
189db3d4 UH	101	*
	102	* The multiplication of the converted value by 0x24 sets the relevant bits in
	103	* both channels and then we mask it out to only affect the channel currently
	104	* requested.
	105	*/
0ab4ea5d	106	static BOOL set_voltage(BYTE channel, BYTE val)
189db3d4	107	{
cc789c14 UH	108	BYTE bits, mask;
	109
	110	switch (val) {
	111	case 1:
	112	bits = 0x24 * 2;
	113	break;
	114	case 2:
	115	bits = 0x24 * 1;
	116	break;
	117	case 5:
	118	bits = 0x24 * 0;
	119	break;
	120	case 10:
	121	bits = 0x24 * 3;
	122	break;
	123	default:
	124	return FALSE;
	125	}
	126
	127	mask = (channel) ? 0xe0 : 0x1c;
	128	IOC = (IOC & ~mask) \| (bits & mask);
189db3d4	129
cc789c14	130	return TRUE;
189db3d4 UH	131	}
189db3d4 UH	132
0ab4ea5d	133	static BOOL set_numchannels(BYTE numchannels)
189db3d4	134	{
cc789c14 UH	135	if (numchannels == 1 \|\| numchannels == 2) {
	136	BYTE fifocfg = 7 + numchannels;
	137	EP2FIFOCFG = fifocfg;
	138	EP6FIFOCFG = fifocfg;
	139	return TRUE;
	140	}
	141
	142	return FALSE;
189db3d4 UH	143	}
189db3d4 UH	144
0ab4ea5d	145	static void clear_fifo(void)
189db3d4	146	{
cc789c14 UH	147	GPIFABORT = 0xff;
	148	SYNCDELAY3;
	149	FIFORESET = 0x80;
	150	SYNCDELAY3;
	151	FIFORESET = 0x82;
	152	SYNCDELAY3;
	153	FIFORESET = 0x86;
	154	SYNCDELAY3;
	155	FIFORESET = 0;
189db3d4 UH	156	}
189db3d4 UH	157
0ab4ea5d	158	static void stop_sampling(void)
189db3d4	159	{
cc789c14 UH	160	GPIFABORT = 0xff;
	161	SYNCDELAY3;
	162	INPKTEND = (altiface == 0) ? 6 : 2;
189db3d4 UH	163	}
189db3d4 UH	164
0ab4ea5d	165	static void start_sampling(void)
189db3d4	166	{
cc789c14 UH	167	int i;
cc789c14 UH	168
be6d306d UH	169	SET_ANALOG_MODE();
be6d306d UH	170
cc789c14 UH	171	clear_fifo();
	172
	173	for (i = 0; i < 1000; i++);
	174
	175	while (!(GPIFTRIG & 0x80))
	176	;
	177
	178	SYNCDELAY3;
	179	GPIFTCB1 = 0x28;
	180	SYNCDELAY3;
	181	GPIFTCB0 = 0;
	182	GPIFTRIG = (altiface == 0) ? 6 : 4;
	183
	184	/* Set green LED, don't clear LED. */
	185	ledcounter = 0;
	186	PC0 = 1;
	187	PC1 = 0;
189db3d4 UH	188	}
189db3d4 UH	189
0ab4ea5d	190	static void select_interface(BYTE alt)
189db3d4	191	{
cc789c14	192	const BYTE *pPacketSize = \
374453b9	193	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
cc789c14 UH	194	+ (9 + (16 * alt) + 9 + 4);
	195
	196	altiface = alt;
	197
	198	if (alt == 0) {
	199	/* Bulk on EP6. */
	200	EP2CFG = 0x00;
	201	EP6CFG = 0xe0;
	202	EP6GPIFFLGSEL = 1;
	203	EP6AUTOINLENL = pPacketSize[0];
	204	EP6AUTOINLENH = pPacketSize[1];
	205	} else {
	206	/* Iso on EP2. */
	207	EP2CFG = 0xd8;
	208	EP6CFG = 0x00;
	209	EP2GPIFFLGSEL = 1;
	210	EP2AUTOINLENL = pPacketSize[0];
	211	EP2AUTOINLENH = pPacketSize[1] & 0x7;
	212	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	213	}
189db3d4 UH	214	}
189db3d4 UH	215
0ab4ea5d	216	static const struct samplerate_info {
cc789c14 UH	217	BYTE rate;
	218	BYTE wait0;
	219	BYTE wait1;
	220	BYTE opc0;
	221	BYTE opc1;
	222	BYTE out0;
	223	BYTE ifcfg;
189db3d4	224	} samplerates[] = {
374453b9 UH	225	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
	226	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
	227	{ 24, 1, 0, 2, 1, 0x40, 0xca },
	228	{ 16, 1, 1, 2, 0, 0x40, 0xca },
	229	{ 12, 2, 1, 2, 0, 0x40, 0xca },
	230	{ 8, 3, 2, 2, 0, 0x40, 0xca },
	231	{ 4, 6, 5, 2, 0, 0x40, 0xca },
	232	{ 2, 12, 11, 2, 0, 0x40, 0xca },
	233	{ 1, 24, 23, 2, 0, 0x40, 0xca },
	234	{ 50, 48, 47, 2, 0, 0x40, 0xca },
	235	{ 20, 120, 119, 2, 0, 0x40, 0xca },
	236	{ 10, 240, 239, 2, 0, 0x40, 0xca },
189db3d4 UH	237	};
189db3d4 UH	238
0ab4ea5d	239	static BOOL set_samplerate(BYTE rate)
189db3d4	240	{
cc789c14 UH	241	BYTE i = 0;
	242
	243	while (samplerates[i].rate != rate) {
	244	i++;
	245	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	246	return FALSE;
	247	}
	248
	249	IFCONFIG = samplerates[i].ifcfg;
	250
	251	AUTOPTRSETUP = 7;
24373950	252	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
cc789c14 UH	253	AUTOPTRL2 = 0x00;
	254
	255	/*
	256	* The program for low-speed, e.g. 1 MHz, is:
3968bbfb UH	257	* wait 24, CTLx=0, FIFO
	258	* wait 23, CTLx=1
	259	* jump 0, CTLx=1
cc789c14 UH	260	*
cc789c14 UH	261	* The program for 24 MHz is:
3968bbfb UH	262	* wait 1, CTLx=0, FIFO
3968bbfb UH	263	* jump 0, CTLx=1
cc789c14 UH	264	*
cc789c14 UH	265	* The program for 30/48 MHz is:
3968bbfb UH	266	* jump 0, CTLx=Z, FIFO, LOOP
	267	*
	268	* (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
cc789c14 UH	269	*/
cc789c14 UH	270
24373950	271	/* LENGTH / BRANCH 0-7 */
cc789c14 UH	272	EXTAUTODAT2 = samplerates[i].wait0;
	273	EXTAUTODAT2 = samplerates[i].wait1;
	274	EXTAUTODAT2 = 1;
	275	EXTAUTODAT2 = 0;
	276	EXTAUTODAT2 = 0;
	277	EXTAUTODAT2 = 0;
	278	EXTAUTODAT2 = 0;
189db3d4	279	EXTAUTODAT2 = 0;
189db3d4	280
24373950	281	/* OPCODE 0-7 */
cc789c14 UH	282	EXTAUTODAT2 = samplerates[i].opc0;
cc789c14 UH	283	EXTAUTODAT2 = samplerates[i].opc1;
24373950	284	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
cc789c14 UH	285	EXTAUTODAT2 = 0;
	286	EXTAUTODAT2 = 0;
	287	EXTAUTODAT2 = 0;
	288	EXTAUTODAT2 = 0;
	289	EXTAUTODAT2 = 0;
	290
24373950	291	/* OUTPUT 0-7 */
cc789c14	292	EXTAUTODAT2 = samplerates[i].out0;
6fcab61f UH	293	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
6fcab61f UH	294	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
24373950 UH	295	EXTAUTODAT2 = 0;
	296	EXTAUTODAT2 = 0;
	297	EXTAUTODAT2 = 0;
	298	EXTAUTODAT2 = 0;
	299	EXTAUTODAT2 = 0;
cc789c14	300
24373950	301	/* LOGIC FUNCTION 0-7 */
cc789c14 UH	302	EXTAUTODAT2 = 0;
	303	EXTAUTODAT2 = 0;
	304	EXTAUTODAT2 = 0;
	305	EXTAUTODAT2 = 0;
	306	EXTAUTODAT2 = 0;
	307	EXTAUTODAT2 = 0;
	308	EXTAUTODAT2 = 0;
	309	EXTAUTODAT2 = 0;
	310
	311	for (i = 0; i < 96; i++)
	312	EXTAUTODAT2 = 0;
	313
	314	return TRUE;
189db3d4	315	}
cc789c14 UH	316
	317	/* Set alt_ifc to the current alt interface for ifc. /
	318	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	319	{
	320	(void)ifc;
	321
	322	*alt_ifc = altiface;
	323
	324	return TRUE;
189db3d4 UH	325	}
189db3d4 UH	326
cc789c14 UH	327	/*
	328	* Return TRUE if you set the interface requested.
	329	*
	330	* Note: This function should reconfigure and reset the endpoints
	331	* according to the interface descriptors you provided.
	332	*/
	333	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	334	{
	335	if (ifc == 0)
	336	select_interface(alt_ifc);
	337
	338	return TRUE;
189db3d4 UH	339	}
189db3d4 UH	340
cc789c14 UH	341	BYTE handle_get_configuration(void)
	342	{
	343	/* We only support configuration 0. */
	344	return 0;
189db3d4 UH	345	}
189db3d4 UH	346
cc789c14 UH	347	BOOL handle_set_configuration(BYTE cfg)
	348	{
	349	/* We only support configuration 0. */
	350	(void)cfg;
	351
189db3d4	352	return TRUE;
189db3d4 UH	353	}
189db3d4 UH	354
cc789c14 UH	355	BOOL handle_vendorcommand(BYTE cmd)
	356	{
	357	stop_sampling();
	358
	359	/* Set red LED. */
	360	PC0 = 0;
	361	PC1 = 1;
	362	ledcounter = 1000;
	363
38e32023 UH	364	/* Clear EP0BCH/L for each valid command. */
38e32023 UH	365	if (cmd >= 0xe0 && cmd <= 0xe4) {
cc789c14 UH	366	EP0BCH = 0;
	367	EP0BCL = 0;
	368	while (EP0CS & bmEPBUSY);
38e32023 UH	369	}
	370
	371	switch (cmd) {
	372	case 0xe0:
	373	case 0xe1:
cc789c14 UH	374	set_voltage(cmd - 0xe0, EP0BUF[0]);
	375	return TRUE;
	376	case 0xe2:
cc789c14 UH	377	set_samplerate(EP0BUF[0]);
	378	return TRUE;
	379	case 0xe3:
cc789c14 UH	380	if (EP0BUF[0] == 1)
	381	start_sampling();
	382	return TRUE;
	383	case 0xe4:
cc789c14 UH	384	set_numchannels(EP0BUF[0]);
	385	return TRUE;
	386	}
	387
	388	return FALSE; /* Not handled by handlers. */
	389	}
	390
0ab4ea5d	391	static void init(void)
cc789c14 UH	392	{
	393	EP4CFG = 0;
	394	EP8CFG = 0;
	395
be6d306d UH	396	SET_ANALOG_MODE();
be6d306d UH	397
cc789c14	398	/* In idle mode tristate all outputs. */
24373950 UH	399	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
24373950 UH	400	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
cc789c14 UH	401	GPIFWFSELECT = 0x00;
	402	GPIFREADYSTAT = 0x00;
	403
	404	stop_sampling();
	405
	406	set_voltage(0, 1);
	407	set_voltage(1, 1);
	408	set_samplerate(1);
	409	set_numchannels(2);
	410	select_interface(0);
189db3d4	411	}
fb4075d5	412
0ab4ea5d	413	static void main(void)
fb4075d5 UH	414	{
	415	/* Save energy. */
	416	SETCPUFREQ(CLK_12M);
	417
	418	init();
	419
	420	/* Set up interrupts. */
	421	USE_USB_INTS();
	422
	423	ENABLE_SUDAV();
	424	ENABLE_USBRESET();
	425	ENABLE_HISPEED();
	426	ENABLE_SUSPEND();
	427	ENABLE_RESUME();
	428
	429	/* Global (8051) interrupt enable. */
	430	EA = 1;
	431
	432	/* Init timer2. */
	433	RCAP2L = -500 & 0xff;
386296a7	434	RCAP2H = (-500 & 0xff00) >> 8;
fb4075d5 UH	435	T2CON = 0;
	436	ET2 = 1;
	437	TR2 = 1;
	438
	439	RENUMERATE();
	440
	441	PORTCCFG = 0;
	442	PORTACFG = 0;
	443	OEC = 0xff;
	444	OEA = 0x80;
	445
	446	while (TRUE) {
	447	if (dosud) {
	448	dosud = FALSE;
	449	handle_setupdata();
	450	}
	451
	452	if (dosuspend) {
	453	dosuspend = FALSE;
	454	do {
	455	/* Make sure ext wakeups are cleared. */
3968bbfb	456	WAKEUPCS \|= bmWU \| bmWU2;
fb4075d5 UH	457	SUSPEND = 1;
	458	PCON \|= 1;
	459	__asm
	460	nop
	461	nop
	462	nop
	463	nop
	464	nop
	465	nop
	466	nop
	467	__endasm;
	468	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	469
	470	/* Resume (TRM 6.4). */
	471	if (REMOTE_WAKEUP()) {
	472	delay(5);
	473	USBCS \|= bmSIGRESUME;
	474	delay(15);
	475	USBCS &= ~bmSIGRESUME;
	476	}
	477	}
	478	}
	479	}