[sigrok-firmware-fx2lafw.git] / hantek_6022be.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

#define SET_ANALOG_MODE()

/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
#define TOGGLE_CALIBRATION_PIN() PA7 = !PA7

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile WORD ledcounter = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	TOGGLE_CALIBRATION_PIN();

	if (ledcounter) {
		if (--ledcounter == 0) {
			/* Clear LED. */
			PC0 = 1;
			PC1 = 1;
		}
	}

	TF2 = 0;
}

/*
 * This sets three bits for each channel, one channel at a time.
 * For channel 0 we want to set bits 5, 6 & 7
 * For channel 1 we want to set bits 2, 3 & 4
 *
 * We convert the input values that are strange due to original
 * firmware code into the value of the three bits as follows:
 *
 * val -> bits
 * 1  -> 010b
 * 2  -> 001b
 * 5  -> 000b
 * 10 -> 011b
 *
 * The third bit is always zero since there are only four outputs connected
 * in the serial selector chip.
 *
 * The multiplication of the converted value by 0x24 sets the relevant bits in
 * both channels and then we mask it out to only affect the channel currently
 * requested.
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits, mask;

	switch (val) {
	case 1:
		bits = 0x24 * 2;
		break;
	case 2:
		bits = 0x24 * 1;
		break;
	case 5:
		bits = 0x24 * 0;
		break;
	case 10:
		bits = 0x24 * 3;
		break;
	default:
		return FALSE;
	}

	mask = (channel) ? 0xe0 : 0x1c;
	IOC = (IOC & ~mask) | (bits & mask);

	return TRUE;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	SET_ANALOG_MODE();

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

	/* Set green LED, don't clear LED. */
	ledcounter = 0;
	PC0 = 1;
	PC1 = 0;
}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, 0x40, 0xca },
	{ 16,    1,   1, 2, 0, 0x40, 0xca },
	{ 12,    2,   1, 2, 0, 0x40, 0xca },
	{  8,    3,   2, 2, 0, 0x40, 0xca },
	{  4,    6,   5, 2, 0, 0x40, 0xca },
	{  2,   12,  11, 2, 0, 0x40, 0xca },
	{  1,   24,  23, 2, 0, 0x40, 0xca },
	{ 50,   48,  47, 2, 0, 0x40, 0xca },
	{ 20,  120, 119, 2, 0, 0x40, 0xca },
	{ 10,  240, 239, 2, 0, 0x40, 0xca },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTLx=0, FIFO
	 * wait 23, CTLx=1
	 * jump 0, CTLx=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTLx=0, FIFO
	 * jump 0, CTLx=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTLx=Z, FIFO, LOOP
	 *
	 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Set red LED. */
	PC0 = 0;
	PC1 = 1;
	ledcounter = 1000;

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe4) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	SET_ANALOG_MODE();

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -500 & 0xff;
	RCAP2H = (-500 & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE();

	PORTCCFG = 0;
	PORTACFG = 0;
	OEC = 0xff;
	OEA = 0x80;

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU | bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
484b3aa0 UH	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
189db3d4 UH	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
040a6eae	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
484b3aa0	19	*/
189db3d4 UH	20
	21	#include <fx2macros.h>
	22	#include <fx2ints.h>
	23	#include <autovector.h>
	24	#include <delay.h>
	25	#include <setupdat.h>
	26
be6d306d UH	27	#define SET_ANALOG_MODE()
be6d306d UH	28
e583c3fc UH	29	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
	30	#define TOGGLE_CALIBRATION_PIN() PA7 = !PA7
	31
cc789c14	32	/* Change to support as many interfaces as you need. */
0ab4ea5d	33	static BYTE altiface = 0;
189db3d4	34
0ab4ea5d	35	static volatile WORD ledcounter = 0;
189db3d4	36
0ab4ea5d UH	37	static volatile __bit dosud = FALSE;
0ab4ea5d UH	38	static volatile __bit dosuspend = FALSE;
cc789c14 UH	39
	40	extern __code BYTE highspd_dscr;
	41	extern __code BYTE fullspd_dscr;
189db3d4	42
cc789c14 UH	43	void resume_isr(void) __interrupt RESUME_ISR
	44	{
	45	CLEAR_RESUME();
189db3d4	46	}
cc789c14 UH	47
	48	void sudav_isr(void) __interrupt SUDAV_ISR
	49	{
	50	dosud = TRUE;
	51	CLEAR_SUDAV();
189db3d4	52	}
cc789c14 UH	53
	54	void usbreset_isr(void) __interrupt USBRESET_ISR
	55	{
	56	handle_hispeed(FALSE);
	57	CLEAR_USBRESET();
189db3d4	58	}
cc789c14 UH	59
	60	void hispeed_isr(void) __interrupt HISPEED_ISR
	61	{
	62	handle_hispeed(TRUE);
	63	CLEAR_HISPEED();
189db3d4 UH	64	}
189db3d4 UH	65
cc789c14 UH	66	void suspend_isr(void) __interrupt SUSPEND_ISR
	67	{
	68	dosuspend = TRUE;
	69	CLEAR_SUSPEND();
189db3d4 UH	70	}
189db3d4 UH	71
cc789c14 UH	72	void timer2_isr(void) __interrupt TF2_ISR
cc789c14 UH	73	{
e583c3fc	74	TOGGLE_CALIBRATION_PIN();
3968bbfb	75
cc789c14 UH	76	if (ledcounter) {
	77	if (--ledcounter == 0) {
	78	/* Clear LED. */
	79	PC0 = 1;
	80	PC1 = 1;
	81	}
	82	}
3968bbfb	83
cc789c14	84	TF2 = 0;
189db3d4	85	}
189db3d4	86
cc789c14 UH	87	/*
cc789c14 UH	88	* This sets three bits for each channel, one channel at a time.
189db3d4 UH	89	* For channel 0 we want to set bits 5, 6 & 7
	90	* For channel 1 we want to set bits 2, 3 & 4
	91	*
cc789c14 UH	92	* We convert the input values that are strange due to original
	93	* firmware code into the value of the three bits as follows:
	94	*
189db3d4 UH	95	* val -> bits
	96	* 1 -> 010b
	97	* 2 -> 001b
	98	* 5 -> 000b
	99	* 10 -> 011b
	100	*
cc789c14 UH	101	* The third bit is always zero since there are only four outputs connected
cc789c14 UH	102	* in the serial selector chip.
189db3d4 UH	103	*
	104	* The multiplication of the converted value by 0x24 sets the relevant bits in
	105	* both channels and then we mask it out to only affect the channel currently
	106	* requested.
	107	*/
0ab4ea5d	108	static BOOL set_voltage(BYTE channel, BYTE val)
189db3d4	109	{
cc789c14 UH	110	BYTE bits, mask;
	111
	112	switch (val) {
	113	case 1:
	114	bits = 0x24 * 2;
	115	break;
	116	case 2:
	117	bits = 0x24 * 1;
	118	break;
	119	case 5:
	120	bits = 0x24 * 0;
	121	break;
	122	case 10:
	123	bits = 0x24 * 3;
	124	break;
	125	default:
	126	return FALSE;
	127	}
	128
	129	mask = (channel) ? 0xe0 : 0x1c;
	130	IOC = (IOC & ~mask) \| (bits & mask);
189db3d4	131
cc789c14	132	return TRUE;
189db3d4 UH	133	}
189db3d4 UH	134
0ab4ea5d	135	static BOOL set_numchannels(BYTE numchannels)
189db3d4	136	{
cc789c14 UH	137	if (numchannels == 1 \|\| numchannels == 2) {
	138	BYTE fifocfg = 7 + numchannels;
	139	EP2FIFOCFG = fifocfg;
	140	EP6FIFOCFG = fifocfg;
	141	return TRUE;
	142	}
	143
	144	return FALSE;
189db3d4 UH	145	}
189db3d4 UH	146
0ab4ea5d	147	static void clear_fifo(void)
189db3d4	148	{
cc789c14 UH	149	GPIFABORT = 0xff;
	150	SYNCDELAY3;
	151	FIFORESET = 0x80;
	152	SYNCDELAY3;
	153	FIFORESET = 0x82;
	154	SYNCDELAY3;
	155	FIFORESET = 0x86;
	156	SYNCDELAY3;
	157	FIFORESET = 0;
189db3d4 UH	158	}
189db3d4 UH	159
0ab4ea5d	160	static void stop_sampling(void)
189db3d4	161	{
cc789c14 UH	162	GPIFABORT = 0xff;
	163	SYNCDELAY3;
	164	INPKTEND = (altiface == 0) ? 6 : 2;
189db3d4 UH	165	}
189db3d4 UH	166
0ab4ea5d	167	static void start_sampling(void)
189db3d4	168	{
cc789c14 UH	169	int i;
cc789c14 UH	170
be6d306d UH	171	SET_ANALOG_MODE();
be6d306d UH	172
cc789c14 UH	173	clear_fifo();
	174
	175	for (i = 0; i < 1000; i++);
	176
	177	while (!(GPIFTRIG & 0x80))
	178	;
	179
	180	SYNCDELAY3;
	181	GPIFTCB1 = 0x28;
	182	SYNCDELAY3;
	183	GPIFTCB0 = 0;
	184	GPIFTRIG = (altiface == 0) ? 6 : 4;
	185
	186	/* Set green LED, don't clear LED. */
	187	ledcounter = 0;
	188	PC0 = 1;
	189	PC1 = 0;
189db3d4 UH	190	}
189db3d4 UH	191
0ab4ea5d	192	static void select_interface(BYTE alt)
189db3d4	193	{
cc789c14	194	const BYTE *pPacketSize = \
374453b9	195	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
cc789c14 UH	196	+ (9 + (16 * alt) + 9 + 4);
	197
	198	altiface = alt;
	199
	200	if (alt == 0) {
	201	/* Bulk on EP6. */
	202	EP2CFG = 0x00;
	203	EP6CFG = 0xe0;
	204	EP6GPIFFLGSEL = 1;
	205	EP6AUTOINLENL = pPacketSize[0];
	206	EP6AUTOINLENH = pPacketSize[1];
	207	} else {
	208	/* Iso on EP2. */
	209	EP2CFG = 0xd8;
	210	EP6CFG = 0x00;
	211	EP2GPIFFLGSEL = 1;
	212	EP2AUTOINLENL = pPacketSize[0];
	213	EP2AUTOINLENH = pPacketSize[1] & 0x7;
	214	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	215	}
189db3d4 UH	216	}
189db3d4 UH	217
0ab4ea5d	218	static const struct samplerate_info {
cc789c14 UH	219	BYTE rate;
	220	BYTE wait0;
	221	BYTE wait1;
	222	BYTE opc0;
	223	BYTE opc1;
	224	BYTE out0;
	225	BYTE ifcfg;
189db3d4	226	} samplerates[] = {
374453b9 UH	227	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
	228	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
	229	{ 24, 1, 0, 2, 1, 0x40, 0xca },
	230	{ 16, 1, 1, 2, 0, 0x40, 0xca },
	231	{ 12, 2, 1, 2, 0, 0x40, 0xca },
	232	{ 8, 3, 2, 2, 0, 0x40, 0xca },
	233	{ 4, 6, 5, 2, 0, 0x40, 0xca },
	234	{ 2, 12, 11, 2, 0, 0x40, 0xca },
	235	{ 1, 24, 23, 2, 0, 0x40, 0xca },
	236	{ 50, 48, 47, 2, 0, 0x40, 0xca },
	237	{ 20, 120, 119, 2, 0, 0x40, 0xca },
	238	{ 10, 240, 239, 2, 0, 0x40, 0xca },
189db3d4 UH	239	};
189db3d4 UH	240
0ab4ea5d	241	static BOOL set_samplerate(BYTE rate)
189db3d4	242	{
cc789c14 UH	243	BYTE i = 0;
	244
	245	while (samplerates[i].rate != rate) {
	246	i++;
	247	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	248	return FALSE;
	249	}
	250
	251	IFCONFIG = samplerates[i].ifcfg;
	252
	253	AUTOPTRSETUP = 7;
24373950	254	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
cc789c14 UH	255	AUTOPTRL2 = 0x00;
	256
	257	/*
	258	* The program for low-speed, e.g. 1 MHz, is:
3968bbfb UH	259	* wait 24, CTLx=0, FIFO
	260	* wait 23, CTLx=1
	261	* jump 0, CTLx=1
cc789c14 UH	262	*
cc789c14 UH	263	* The program for 24 MHz is:
3968bbfb UH	264	* wait 1, CTLx=0, FIFO
3968bbfb UH	265	* jump 0, CTLx=1
cc789c14 UH	266	*
cc789c14 UH	267	* The program for 30/48 MHz is:
3968bbfb UH	268	* jump 0, CTLx=Z, FIFO, LOOP
	269	*
	270	* (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
cc789c14 UH	271	*/
cc789c14 UH	272
24373950	273	/* LENGTH / BRANCH 0-7 */
cc789c14 UH	274	EXTAUTODAT2 = samplerates[i].wait0;
	275	EXTAUTODAT2 = samplerates[i].wait1;
	276	EXTAUTODAT2 = 1;
	277	EXTAUTODAT2 = 0;
	278	EXTAUTODAT2 = 0;
	279	EXTAUTODAT2 = 0;
	280	EXTAUTODAT2 = 0;
189db3d4	281	EXTAUTODAT2 = 0;
189db3d4	282
24373950	283	/* OPCODE 0-7 */
cc789c14 UH	284	EXTAUTODAT2 = samplerates[i].opc0;
cc789c14 UH	285	EXTAUTODAT2 = samplerates[i].opc1;
24373950	286	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
cc789c14 UH	287	EXTAUTODAT2 = 0;
	288	EXTAUTODAT2 = 0;
	289	EXTAUTODAT2 = 0;
	290	EXTAUTODAT2 = 0;
	291	EXTAUTODAT2 = 0;
	292
24373950	293	/* OUTPUT 0-7 */
cc789c14	294	EXTAUTODAT2 = samplerates[i].out0;
6fcab61f UH	295	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
6fcab61f UH	296	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
24373950 UH	297	EXTAUTODAT2 = 0;
	298	EXTAUTODAT2 = 0;
	299	EXTAUTODAT2 = 0;
	300	EXTAUTODAT2 = 0;
	301	EXTAUTODAT2 = 0;
cc789c14	302
24373950	303	/* LOGIC FUNCTION 0-7 */
cc789c14 UH	304	EXTAUTODAT2 = 0;
	305	EXTAUTODAT2 = 0;
	306	EXTAUTODAT2 = 0;
	307	EXTAUTODAT2 = 0;
	308	EXTAUTODAT2 = 0;
	309	EXTAUTODAT2 = 0;
	310	EXTAUTODAT2 = 0;
	311	EXTAUTODAT2 = 0;
	312
	313	for (i = 0; i < 96; i++)
	314	EXTAUTODAT2 = 0;
	315
	316	return TRUE;
189db3d4	317	}
cc789c14 UH	318
	319	/* Set alt_ifc to the current alt interface for ifc. /
	320	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	321	{
	322	(void)ifc;
	323
	324	*alt_ifc = altiface;
	325
	326	return TRUE;
189db3d4 UH	327	}
189db3d4 UH	328
cc789c14 UH	329	/*
	330	* Return TRUE if you set the interface requested.
	331	*
	332	* Note: This function should reconfigure and reset the endpoints
	333	* according to the interface descriptors you provided.
	334	*/
	335	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	336	{
	337	if (ifc == 0)
	338	select_interface(alt_ifc);
	339
	340	return TRUE;
189db3d4 UH	341	}
189db3d4 UH	342
cc789c14 UH	343	BYTE handle_get_configuration(void)
	344	{
	345	/* We only support configuration 0. */
	346	return 0;
189db3d4 UH	347	}
189db3d4 UH	348
cc789c14 UH	349	BOOL handle_set_configuration(BYTE cfg)
	350	{
	351	/* We only support configuration 0. */
	352	(void)cfg;
	353
189db3d4	354	return TRUE;
189db3d4 UH	355	}
189db3d4 UH	356
cc789c14 UH	357	BOOL handle_vendorcommand(BYTE cmd)
	358	{
	359	stop_sampling();
	360
	361	/* Set red LED. */
	362	PC0 = 0;
	363	PC1 = 1;
	364	ledcounter = 1000;
	365
38e32023 UH	366	/* Clear EP0BCH/L for each valid command. */
38e32023 UH	367	if (cmd >= 0xe0 && cmd <= 0xe4) {
cc789c14 UH	368	EP0BCH = 0;
	369	EP0BCL = 0;
	370	while (EP0CS & bmEPBUSY);
38e32023 UH	371	}
	372
	373	switch (cmd) {
	374	case 0xe0:
	375	case 0xe1:
cc789c14 UH	376	set_voltage(cmd - 0xe0, EP0BUF[0]);
	377	return TRUE;
	378	case 0xe2:
cc789c14 UH	379	set_samplerate(EP0BUF[0]);
	380	return TRUE;
	381	case 0xe3:
cc789c14 UH	382	if (EP0BUF[0] == 1)
	383	start_sampling();
	384	return TRUE;
	385	case 0xe4:
cc789c14 UH	386	set_numchannels(EP0BUF[0]);
	387	return TRUE;
	388	}
	389
	390	return FALSE; /* Not handled by handlers. */
	391	}
	392
0ab4ea5d	393	static void init(void)
cc789c14 UH	394	{
	395	EP4CFG = 0;
	396	EP8CFG = 0;
	397
be6d306d UH	398	SET_ANALOG_MODE();
be6d306d UH	399
cc789c14	400	/* In idle mode tristate all outputs. */
24373950 UH	401	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
24373950 UH	402	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
cc789c14 UH	403	GPIFWFSELECT = 0x00;
	404	GPIFREADYSTAT = 0x00;
	405
	406	stop_sampling();
	407
	408	set_voltage(0, 1);
	409	set_voltage(1, 1);
	410	set_samplerate(1);
	411	set_numchannels(2);
	412	select_interface(0);
189db3d4	413	}
fb4075d5	414
0ab4ea5d	415	static void main(void)
fb4075d5 UH	416	{
	417	/* Save energy. */
	418	SETCPUFREQ(CLK_12M);
	419
	420	init();
	421
	422	/* Set up interrupts. */
	423	USE_USB_INTS();
	424
	425	ENABLE_SUDAV();
	426	ENABLE_USBRESET();
	427	ENABLE_HISPEED();
	428	ENABLE_SUSPEND();
	429	ENABLE_RESUME();
	430
	431	/* Global (8051) interrupt enable. */
	432	EA = 1;
	433
	434	/* Init timer2. */
	435	RCAP2L = -500 & 0xff;
386296a7	436	RCAP2H = (-500 & 0xff00) >> 8;
fb4075d5 UH	437	T2CON = 0;
	438	ET2 = 1;
	439	TR2 = 1;
	440
	441	RENUMERATE();
	442
	443	PORTCCFG = 0;
	444	PORTACFG = 0;
	445	OEC = 0xff;
	446	OEA = 0x80;
	447
	448	while (TRUE) {
	449	if (dosud) {
	450	dosud = FALSE;
	451	handle_setupdata();
	452	}
	453
	454	if (dosuspend) {
	455	dosuspend = FALSE;
	456	do {
	457	/* Make sure ext wakeups are cleared. */
3968bbfb	458	WAKEUPCS \|= bmWU \| bmWU2;
fb4075d5 UH	459	SUSPEND = 1;
	460	PCON \|= 1;
	461	__asm
	462	nop
	463	nop
	464	nop
	465	nop
	466	nop
	467	nop
	468	nop
	469	__endasm;
	470	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	471
	472	/* Resume (TRM 6.4). */
	473	if (REMOTE_WAKEUP()) {
	474	delay(5);
	475	USBCS \|= bmSIGRESUME;
	476	delay(15);
	477	USBCS &= ~bmSIGRESUME;
	478	}
	479	}
	480	}
	481	}