[sigrok-firmware-fx2lafw.git] / hantek_6022be.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile WORD ledcounter = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
	PA7 = !PA7;

	if (ledcounter) {
		if (--ledcounter == 0) {
			/* Clear LED. */
			PC0 = 1;
			PC1 = 1;
		}
	}

	TF2 = 0;
}

/*
 * This sets three bits for each channel, one channel at a time.
 * For channel 0 we want to set bits 5, 6 & 7
 * For channel 1 we want to set bits 2, 3 & 4
 *
 * We convert the input values that are strange due to original
 * firmware code into the value of the three bits as follows:
 *
 * val -> bits
 * 1  -> 010b
 * 2  -> 001b
 * 5  -> 000b
 * 10 -> 011b
 *
 * The third bit is always zero since there are only four outputs connected
 * in the serial selector chip.
 *
 * The multiplication of the converted value by 0x24 sets the relevant bits in
 * both channels and then we mask it out to only affect the channel currently
 * requested.
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits, mask;

	switch (val) {
	case 1:
		bits = 0x24 * 2;
		break;
	case 2:
		bits = 0x24 * 1;
		break;
	case 5:
		bits = 0x24 * 0;
		break;
	case 10:
		bits = 0x24 * 3;
		break;
	default:
		return FALSE;
	}

	mask = (channel) ? 0xe0 : 0x1c;
	IOC = (IOC & ~mask) | (bits & mask);

	return TRUE;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

	/* Set green LED, don't clear LED. */
	ledcounter = 0;
	PC0 = 1;
	PC1 = 0;
}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, 0x40, 0xca },
	{ 16,    1,   1, 2, 0, 0x40, 0xca },
	{ 12,    2,   1, 2, 0, 0x40, 0xca },
	{  8,    3,   2, 2, 0, 0x40, 0xca },
	{  4,    6,   5, 2, 0, 0x40, 0xca },
	{  2,   12,  11, 2, 0, 0x40, 0xca },
	{  1,   24,  23, 2, 0, 0x40, 0xca },
	{ 50,   48,  47, 2, 0, 0x40, 0xca },
	{ 20,  120, 119, 2, 0, 0x40, 0xca },
	{ 10,  240, 239, 2, 0, 0x40, 0xca },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTLx=0, FIFO
	 * wait 23, CTLx=1
	 * jump 0, CTLx=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTLx=0, FIFO
	 * jump 0, CTLx=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTLx=Z, FIFO, LOOP
	 *
	 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Set red LED. */
	PC0 = 0;
	PC1 = 1;
	ledcounter = 1000;

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe4) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -500 & 0xff;
	RCAP2H = (-500 & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE();

	PORTCCFG = 0;
	PORTACFG = 0;
	OEC = 0xff;
	OEA = 0x80;

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU | bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
484b3aa0 UH	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
189db3d4 UH	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
040a6eae	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
484b3aa0	19	*/
189db3d4 UH	20
	21	#include <fx2macros.h>
	22	#include <fx2ints.h>
	23	#include <autovector.h>
	24	#include <delay.h>
	25	#include <setupdat.h>
	26
cc789c14	27	/* Change to support as many interfaces as you need. */
0ab4ea5d	28	static BYTE altiface = 0;
189db3d4	29
0ab4ea5d	30	static volatile WORD ledcounter = 0;
189db3d4	31
0ab4ea5d UH	32	static volatile __bit dosud = FALSE;
0ab4ea5d UH	33	static volatile __bit dosuspend = FALSE;
cc789c14 UH	34
	35	extern __code BYTE highspd_dscr;
	36	extern __code BYTE fullspd_dscr;
189db3d4	37
cc789c14 UH	38	void resume_isr(void) __interrupt RESUME_ISR
	39	{
	40	CLEAR_RESUME();
189db3d4	41	}
cc789c14 UH	42
	43	void sudav_isr(void) __interrupt SUDAV_ISR
	44	{
	45	dosud = TRUE;
	46	CLEAR_SUDAV();
189db3d4	47	}
cc789c14 UH	48
	49	void usbreset_isr(void) __interrupt USBRESET_ISR
	50	{
	51	handle_hispeed(FALSE);
	52	CLEAR_USBRESET();
189db3d4	53	}
cc789c14 UH	54
	55	void hispeed_isr(void) __interrupt HISPEED_ISR
	56	{
	57	handle_hispeed(TRUE);
	58	CLEAR_HISPEED();
189db3d4 UH	59	}
189db3d4 UH	60
cc789c14 UH	61	void suspend_isr(void) __interrupt SUSPEND_ISR
	62	{
	63	dosuspend = TRUE;
	64	CLEAR_SUSPEND();
189db3d4 UH	65	}
189db3d4 UH	66
cc789c14 UH	67	void timer2_isr(void) __interrupt TF2_ISR
cc789c14 UH	68	{
3968bbfb	69	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
cc789c14	70	PA7 = !PA7;
3968bbfb	71
cc789c14 UH	72	if (ledcounter) {
	73	if (--ledcounter == 0) {
	74	/* Clear LED. */
	75	PC0 = 1;
	76	PC1 = 1;
	77	}
	78	}
3968bbfb	79
cc789c14	80	TF2 = 0;
189db3d4	81	}
189db3d4	82
cc789c14 UH	83	/*
cc789c14 UH	84	* This sets three bits for each channel, one channel at a time.
189db3d4 UH	85	* For channel 0 we want to set bits 5, 6 & 7
	86	* For channel 1 we want to set bits 2, 3 & 4
	87	*
cc789c14 UH	88	* We convert the input values that are strange due to original
	89	* firmware code into the value of the three bits as follows:
	90	*
189db3d4 UH	91	* val -> bits
	92	* 1 -> 010b
	93	* 2 -> 001b
	94	* 5 -> 000b
	95	* 10 -> 011b
	96	*
cc789c14 UH	97	* The third bit is always zero since there are only four outputs connected
cc789c14 UH	98	* in the serial selector chip.
189db3d4 UH	99	*
	100	* The multiplication of the converted value by 0x24 sets the relevant bits in
	101	* both channels and then we mask it out to only affect the channel currently
	102	* requested.
	103	*/
0ab4ea5d	104	static BOOL set_voltage(BYTE channel, BYTE val)
189db3d4	105	{
cc789c14 UH	106	BYTE bits, mask;
	107
	108	switch (val) {
	109	case 1:
	110	bits = 0x24 * 2;
	111	break;
	112	case 2:
	113	bits = 0x24 * 1;
	114	break;
	115	case 5:
	116	bits = 0x24 * 0;
	117	break;
	118	case 10:
	119	bits = 0x24 * 3;
	120	break;
	121	default:
	122	return FALSE;
	123	}
	124
	125	mask = (channel) ? 0xe0 : 0x1c;
	126	IOC = (IOC & ~mask) \| (bits & mask);
189db3d4	127
cc789c14	128	return TRUE;
189db3d4 UH	129	}
189db3d4 UH	130
0ab4ea5d	131	static BOOL set_numchannels(BYTE numchannels)
189db3d4	132	{
cc789c14 UH	133	if (numchannels == 1 \|\| numchannels == 2) {
	134	BYTE fifocfg = 7 + numchannels;
	135	EP2FIFOCFG = fifocfg;
	136	EP6FIFOCFG = fifocfg;
	137	return TRUE;
	138	}
	139
	140	return FALSE;
189db3d4 UH	141	}
189db3d4 UH	142
0ab4ea5d	143	static void clear_fifo(void)
189db3d4	144	{
cc789c14 UH	145	GPIFABORT = 0xff;
	146	SYNCDELAY3;
	147	FIFORESET = 0x80;
	148	SYNCDELAY3;
	149	FIFORESET = 0x82;
	150	SYNCDELAY3;
	151	FIFORESET = 0x86;
	152	SYNCDELAY3;
	153	FIFORESET = 0;
189db3d4 UH	154	}
189db3d4 UH	155
0ab4ea5d	156	static void stop_sampling(void)
189db3d4	157	{
cc789c14 UH	158	GPIFABORT = 0xff;
	159	SYNCDELAY3;
	160	INPKTEND = (altiface == 0) ? 6 : 2;
189db3d4 UH	161	}
189db3d4 UH	162
0ab4ea5d	163	static void start_sampling(void)
189db3d4	164	{
cc789c14 UH	165	int i;
	166
	167	clear_fifo();
	168
	169	for (i = 0; i < 1000; i++);
	170
	171	while (!(GPIFTRIG & 0x80))
	172	;
	173
	174	SYNCDELAY3;
	175	GPIFTCB1 = 0x28;
	176	SYNCDELAY3;
	177	GPIFTCB0 = 0;
	178	GPIFTRIG = (altiface == 0) ? 6 : 4;
	179
	180	/* Set green LED, don't clear LED. */
	181	ledcounter = 0;
	182	PC0 = 1;
	183	PC1 = 0;
189db3d4 UH	184	}
189db3d4 UH	185
0ab4ea5d	186	static void select_interface(BYTE alt)
189db3d4	187	{
cc789c14	188	const BYTE *pPacketSize = \
374453b9	189	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
cc789c14 UH	190	+ (9 + (16 * alt) + 9 + 4);
	191
	192	altiface = alt;
	193
	194	if (alt == 0) {
	195	/* Bulk on EP6. */
	196	EP2CFG = 0x00;
	197	EP6CFG = 0xe0;
	198	EP6GPIFFLGSEL = 1;
	199	EP6AUTOINLENL = pPacketSize[0];
	200	EP6AUTOINLENH = pPacketSize[1];
	201	} else {
	202	/* Iso on EP2. */
	203	EP2CFG = 0xd8;
	204	EP6CFG = 0x00;
	205	EP2GPIFFLGSEL = 1;
	206	EP2AUTOINLENL = pPacketSize[0];
	207	EP2AUTOINLENH = pPacketSize[1] & 0x7;
	208	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	209	}
189db3d4 UH	210	}
189db3d4 UH	211
0ab4ea5d	212	static const struct samplerate_info {
cc789c14 UH	213	BYTE rate;
	214	BYTE wait0;
	215	BYTE wait1;
	216	BYTE opc0;
	217	BYTE opc1;
	218	BYTE out0;
	219	BYTE ifcfg;
189db3d4	220	} samplerates[] = {
374453b9 UH	221	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
	222	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
	223	{ 24, 1, 0, 2, 1, 0x40, 0xca },
	224	{ 16, 1, 1, 2, 0, 0x40, 0xca },
	225	{ 12, 2, 1, 2, 0, 0x40, 0xca },
	226	{ 8, 3, 2, 2, 0, 0x40, 0xca },
	227	{ 4, 6, 5, 2, 0, 0x40, 0xca },
	228	{ 2, 12, 11, 2, 0, 0x40, 0xca },
	229	{ 1, 24, 23, 2, 0, 0x40, 0xca },
	230	{ 50, 48, 47, 2, 0, 0x40, 0xca },
	231	{ 20, 120, 119, 2, 0, 0x40, 0xca },
	232	{ 10, 240, 239, 2, 0, 0x40, 0xca },
189db3d4 UH	233	};
189db3d4 UH	234
0ab4ea5d	235	static BOOL set_samplerate(BYTE rate)
189db3d4	236	{
cc789c14 UH	237	BYTE i = 0;
	238
	239	while (samplerates[i].rate != rate) {
	240	i++;
	241	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	242	return FALSE;
	243	}
	244
	245	IFCONFIG = samplerates[i].ifcfg;
	246
	247	AUTOPTRSETUP = 7;
24373950	248	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
cc789c14 UH	249	AUTOPTRL2 = 0x00;
	250
	251	/*
	252	* The program for low-speed, e.g. 1 MHz, is:
3968bbfb UH	253	* wait 24, CTLx=0, FIFO
	254	* wait 23, CTLx=1
	255	* jump 0, CTLx=1
cc789c14 UH	256	*
cc789c14 UH	257	* The program for 24 MHz is:
3968bbfb UH	258	* wait 1, CTLx=0, FIFO
3968bbfb UH	259	* jump 0, CTLx=1
cc789c14 UH	260	*
cc789c14 UH	261	* The program for 30/48 MHz is:
3968bbfb UH	262	* jump 0, CTLx=Z, FIFO, LOOP
	263	*
	264	* (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
cc789c14 UH	265	*/
cc789c14 UH	266
24373950	267	/* LENGTH / BRANCH 0-7 */
cc789c14 UH	268	EXTAUTODAT2 = samplerates[i].wait0;
	269	EXTAUTODAT2 = samplerates[i].wait1;
	270	EXTAUTODAT2 = 1;
	271	EXTAUTODAT2 = 0;
	272	EXTAUTODAT2 = 0;
	273	EXTAUTODAT2 = 0;
	274	EXTAUTODAT2 = 0;
189db3d4	275	EXTAUTODAT2 = 0;
189db3d4	276
24373950	277	/* OPCODE 0-7 */
cc789c14 UH	278	EXTAUTODAT2 = samplerates[i].opc0;
cc789c14 UH	279	EXTAUTODAT2 = samplerates[i].opc1;
24373950	280	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
cc789c14 UH	281	EXTAUTODAT2 = 0;
	282	EXTAUTODAT2 = 0;
	283	EXTAUTODAT2 = 0;
	284	EXTAUTODAT2 = 0;
	285	EXTAUTODAT2 = 0;
	286
24373950	287	/* OUTPUT 0-7 */
cc789c14	288	EXTAUTODAT2 = samplerates[i].out0;
6fcab61f UH	289	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
6fcab61f UH	290	EXTAUTODAT2 = 0x44; /* OE2=1, CTL2=1 */
24373950 UH	291	EXTAUTODAT2 = 0;
	292	EXTAUTODAT2 = 0;
	293	EXTAUTODAT2 = 0;
	294	EXTAUTODAT2 = 0;
	295	EXTAUTODAT2 = 0;
cc789c14	296
24373950	297	/* LOGIC FUNCTION 0-7 */
cc789c14 UH	298	EXTAUTODAT2 = 0;
	299	EXTAUTODAT2 = 0;
	300	EXTAUTODAT2 = 0;
	301	EXTAUTODAT2 = 0;
	302	EXTAUTODAT2 = 0;
	303	EXTAUTODAT2 = 0;
	304	EXTAUTODAT2 = 0;
	305	EXTAUTODAT2 = 0;
	306
	307	for (i = 0; i < 96; i++)
	308	EXTAUTODAT2 = 0;
	309
	310	return TRUE;
189db3d4	311	}
cc789c14 UH	312
	313	/* Set alt_ifc to the current alt interface for ifc. /
	314	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	315	{
	316	(void)ifc;
	317
	318	*alt_ifc = altiface;
	319
	320	return TRUE;
189db3d4 UH	321	}
189db3d4 UH	322
cc789c14 UH	323	/*
	324	* Return TRUE if you set the interface requested.
	325	*
	326	* Note: This function should reconfigure and reset the endpoints
	327	* according to the interface descriptors you provided.
	328	*/
	329	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	330	{
	331	if (ifc == 0)
	332	select_interface(alt_ifc);
	333
	334	return TRUE;
189db3d4 UH	335	}
189db3d4 UH	336
cc789c14 UH	337	BYTE handle_get_configuration(void)
	338	{
	339	/* We only support configuration 0. */
	340	return 0;
189db3d4 UH	341	}
189db3d4 UH	342
cc789c14 UH	343	BOOL handle_set_configuration(BYTE cfg)
	344	{
	345	/* We only support configuration 0. */
	346	(void)cfg;
	347
189db3d4	348	return TRUE;
189db3d4 UH	349	}
189db3d4 UH	350
cc789c14 UH	351	BOOL handle_vendorcommand(BYTE cmd)
	352	{
	353	stop_sampling();
	354
	355	/* Set red LED. */
	356	PC0 = 0;
	357	PC1 = 1;
	358	ledcounter = 1000;
	359
38e32023 UH	360	/* Clear EP0BCH/L for each valid command. */
38e32023 UH	361	if (cmd >= 0xe0 && cmd <= 0xe4) {
cc789c14 UH	362	EP0BCH = 0;
	363	EP0BCL = 0;
	364	while (EP0CS & bmEPBUSY);
38e32023 UH	365	}
	366
	367	switch (cmd) {
	368	case 0xe0:
	369	case 0xe1:
cc789c14 UH	370	set_voltage(cmd - 0xe0, EP0BUF[0]);
	371	return TRUE;
	372	case 0xe2:
cc789c14 UH	373	set_samplerate(EP0BUF[0]);
	374	return TRUE;
	375	case 0xe3:
cc789c14 UH	376	if (EP0BUF[0] == 1)
	377	start_sampling();
	378	return TRUE;
	379	case 0xe4:
cc789c14 UH	380	set_numchannels(EP0BUF[0]);
	381	return TRUE;
	382	}
	383
	384	return FALSE; /* Not handled by handlers. */
	385	}
	386
0ab4ea5d	387	static void init(void)
cc789c14 UH	388	{
	389	EP4CFG = 0;
	390	EP8CFG = 0;
	391
	392	/* In idle mode tristate all outputs. */
24373950 UH	393	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
24373950 UH	394	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
cc789c14 UH	395	GPIFWFSELECT = 0x00;
	396	GPIFREADYSTAT = 0x00;
	397
	398	stop_sampling();
	399
	400	set_voltage(0, 1);
	401	set_voltage(1, 1);
	402	set_samplerate(1);
	403	set_numchannels(2);
	404	select_interface(0);
189db3d4	405	}
fb4075d5	406
0ab4ea5d	407	static void main(void)
fb4075d5 UH	408	{
	409	/* Save energy. */
	410	SETCPUFREQ(CLK_12M);
	411
	412	init();
	413
	414	/* Set up interrupts. */
	415	USE_USB_INTS();
	416
	417	ENABLE_SUDAV();
	418	ENABLE_USBRESET();
	419	ENABLE_HISPEED();
	420	ENABLE_SUSPEND();
	421	ENABLE_RESUME();
	422
	423	/* Global (8051) interrupt enable. */
	424	EA = 1;
	425
	426	/* Init timer2. */
	427	RCAP2L = -500 & 0xff;
386296a7	428	RCAP2H = (-500 & 0xff00) >> 8;
fb4075d5 UH	429	T2CON = 0;
	430	ET2 = 1;
	431	TR2 = 1;
	432
	433	RENUMERATE();
	434
	435	PORTCCFG = 0;
	436	PORTACFG = 0;
	437	OEC = 0xff;
	438	OEA = 0x80;
	439
	440	while (TRUE) {
	441	if (dosud) {
	442	dosud = FALSE;
	443	handle_setupdata();
	444	}
	445
	446	if (dosuspend) {
	447	dosuspend = FALSE;
	448	do {
	449	/* Make sure ext wakeups are cleared. */
3968bbfb	450	WAKEUPCS \|= bmWU \| bmWU2;
fb4075d5 UH	451	SUSPEND = 1;
	452	PCON \|= 1;
	453	__asm
	454	nop
	455	nop
	456	nop
	457	nop
	458	nop
	459	nop
	460	nop
	461	__endasm;
	462	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	463
	464	/* Resume (TRM 6.4). */
	465	if (REMOTE_WAKEUP()) {
	466	delay(5);
	467	USBCS \|= bmSIGRESUME;
	468	delay(15);
	469	USBCS &= ~bmSIGRESUME;
	470	}
	471	}
	472	}
	473	}