]> sigrok.org Git - libsigrokdecode.git/commitdiff
usb_signalling: Move another edge detection to common backend code
authorGerhard Sittig <redacted>
Sun, 18 Jun 2017 13:51:35 +0000 (15:51 +0200)
committerGerhard Sittig <redacted>
Tue, 20 Jun 2017 21:10:14 +0000 (23:10 +0200)
Rephrase how the 'WAIT IDLE' stage skips over all-low input signals.
Have the next high level on either line detected in common code.

decoders/usb_signalling/pd.py

index c0e0141d7dcfd5554d3b10ece73180b3278ed968..ae0f651a5de5a2ed384585a58a36b9b8992b65a7 100644 (file)
@@ -329,9 +329,10 @@ class Decoder(srd.Decoder):
                 elif self.state == 'GET EOP':
                     self.get_eop(sym)
             elif self.state == 'WAIT IDLE':
+                # Skip "all-low" input. Wait for high level on either DP or DM.
                 pins = self.wait({'skip': 1})
-                if pins == (0, 0):
-                    continue
+                while not pins[0] and not pins[1]:
+                    pins = self.wait([{0: 'h'}, {1: 'h'}])
                 if self.samplenum - self.samplenum_lastedge > 1:
                     sym = symbols[self.options['signalling']][pins]
                     self.handle_idle(sym)