- self.oldsck = sck
-
- # Sample data on rising/falling clock edge (depends on mode).
- mode = spi_mode[self.options['cpol'], self.options['cpha']]
- if mode == 0 and sck == 0: # Sample on rising clock edge
- continue
- elif mode == 1 and sck == 1: # Sample on falling clock edge
- continue
- elif mode == 2 and sck == 1: # Sample on falling clock edge
- continue
- elif mode == 3 and sck == 0: # Sample on rising clock edge
- continue
-
- # If this is the first bit, save its sample number.
- if self.bitcount == 0:
- self.startsample = self.samplenum
- active_low = (self.options['cs_polarity'] == 'active-low')
- deasserted = cs if active_low else not cs
- if deasserted:
- self.cs_was_deasserted_during_data_word = 1
-
- ws = self.options['wordsize']
-
- # Receive MOSI bit into our shift register.
- if self.options['bitorder'] == 'msb-first':
- self.mosidata |= mosi << (ws - 1 - self.bitcount)
- else:
- self.mosidata |= mosi << self.bitcount