2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 # USB signalling (low-speed and full-speed) protocol decoder
24 import sigrokdecode as srd
26 # Low-/full-speed symbols.
27 # Note: Low-speed J and K are inverted compared to the full-speed J and K!
30 # (<dp>, <dm>): <symbol/state>
37 # (<dp>, <dm>): <symbol/state>
46 'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
47 'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
50 class Decoder(srd.Decoder):
53 name = 'USB signalling'
54 longname = 'Universal Serial Bus (LS/FS) signalling'
55 desc = 'USB (low-speed and full-speed) signalling protocol.'
58 outputs = ['usb_signalling']
60 {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
61 {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
65 'signalling': ['Signalling', 'full-speed'],
68 ['Text', 'Human-readable text'],
72 self.oldsym = 'J' # The "idle" state is J.
80 self.samplenum_target = None
82 self.consecutive_ones = 0
85 def start(self, metadata):
86 self.out_proto = self.add(srd.OUTPUT_PROTO, 'usb_signalling')
87 self.out_ann = self.add(srd.OUTPUT_ANN, 'usb_signalling')
88 self.bitrate = bitrates[self.options['signalling']]
89 self.bitwidth = float(metadata['samplerate']) / float(self.bitrate)
94 def putpx(self, data):
95 self.put(self.samplenum, self.samplenum, self.out_proto, data)
98 self.put(self.samplenum, self.samplenum, self.out_ann, data)
100 def putpb(self, data):
101 s, halfbit = self.samplenum, int(self.bitwidth / 2)
102 self.put(s - halfbit, s + halfbit, self.out_proto, data)
104 def putb(self, data):
105 s, halfbit = self.samplenum, int(self.bitwidth / 2)
106 self.put(s - halfbit, s + halfbit, self.out_ann, data)
108 def set_new_target_samplenum(self):
109 bitpos = self.ss_sop + (self.bitwidth / 2)
110 bitpos += self.bitnum * self.bitwidth
111 self.samplenum_target = int(bitpos)
113 def wait_for_sop(self, sym):
114 # Wait for a Start of Packet (SOP), i.e. a J->K symbol change.
118 self.ss_sop = self.samplenum
119 self.set_new_target_samplenum()
120 self.putpx(['SOP', None])
121 self.putx([0, ['SOP']])
122 self.state = 'GET BIT'
124 def handle_bit(self, sym, b):
125 if self.consecutive_ones == 6 and b == '0':
126 # Stuff bit. Don't add to the packet, reset self.consecutive_ones.
127 self.putb([0, ['SB: %s/%s' % (sym, b)]])
128 self.consecutive_ones = 0
130 # Normal bit. Add it to the packet, update self.consecutive_ones.
131 self.putb([0, ['%s/%s' % (sym, b)]])
134 self.consecutive_ones += 1
136 self.consecutive_ones = 0
138 def get_eop(self, sym):
139 # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
140 self.syms.append(sym)
141 self.putpb(['SYM', sym])
142 self.putb([0, ['%s' % sym]])
144 self.set_new_target_samplenum()
146 if self.syms[-2:] == ['SE0', 'J']:
147 # Got an EOP, i.e. we now have a full packet.
148 self.putpb(['PACKET', self.packet])
149 self.putb([0, ['PACKET: %s' % self.packet]])
150 self.bitnum, self.packet, self.syms, self.state = 0, '', [], 'IDLE'
151 self.consecutive_ones = 0
153 def get_bit(self, sym):
155 # Start of an EOP. Change state, run get_eop() for this bit.
156 self.state = 'GET EOP'
159 self.syms.append(sym)
160 self.putpb(['SYM', sym])
161 b = '0' if self.oldsym != sym else '1'
162 self.handle_bit(sym, b)
164 self.set_new_target_samplenum()
167 def decode(self, ss, es, data):
168 for (self.samplenum, pins) in data:
170 if self.state == 'IDLE':
171 # Ignore identical samples early on (for performance reasons).
172 if self.oldpins == pins:
175 sym = symbols[self.options['signalling']][tuple(pins)]
176 self.wait_for_sop(sym)
177 elif self.state in ('GET BIT', 'GET EOP'):
178 # Wait until we're in the middle of the desired bit.
179 if self.samplenum < self.samplenum_target:
181 sym = symbols[self.options['signalling']][tuple(pins)]
182 if self.state == 'GET BIT':
184 elif self.state == 'GET EOP':
187 raise Exception('Invalid state: %s' % self.state)