2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011-2014 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 import sigrokdecode as srd
21 from common.srdhelper import bitpack
22 from math import floor, ceil
28 [<ptype>, <rxtx>, <pdata>]
30 This is the list of <ptype>s and their respective <pdata> values:
31 - 'STARTBIT': The data is the (integer) value of the start bit (0/1).
32 - 'DATA': This is always a tuple containing two items:
33 - 1st item: the (integer) value of the UART data. Valid values
34 range from 0 to 511 (as the data can be up to 9 bits in size).
35 - 2nd item: the list of individual data bits and their ss/es numbers.
36 - 'PARITYBIT': The data is the (integer) value of the parity bit (0/1).
37 - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1).
38 - 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1).
39 - 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1).
40 - 'PARITY ERROR': The data is a tuple with two entries. The first one is
41 the expected parity value, the second is the actual parity value.
42 - 'BREAK': The data is always 0.
43 - 'FRAME': The data is always a tuple containing two items: The (integer)
44 value of the UART data, and a boolean which reflects the validity of the
46 - 'IDLE': The data is always 0.
48 The <rxtx> field is 0 for RX packets, 1 for TX packets.
51 # Used for differentiating between the two data directions.
55 # Given a parity type to check (odd, even, zero, one), the value of the
56 # parity bit, the value of the data, and the length of the data (5-9 bits,
57 # usually 8 bits) return True if the parity is correct, False otherwise.
58 # 'none' is _not_ allowed as value for 'parity_type'.
59 def parity_ok(parity_type, parity_bit, data, data_bits):
61 if parity_type == 'ignore':
64 # Handle easy cases first (parity bit is always 1 or 0).
65 if parity_type == 'zero':
66 return parity_bit == 0
67 elif parity_type == 'one':
68 return parity_bit == 1
70 # Count number of 1 (high) bits in the data (and the parity bit itself!).
71 ones = bin(data).count('1') + parity_bit
73 # Check for odd/even parity.
74 if parity_type == 'odd':
75 return (ones % 2) == 1
76 elif parity_type == 'even':
77 return (ones % 2) == 0
79 class SamplerateError(Exception):
82 class ChannelError(Exception):
86 RX_DATA, TX_DATA, RX_START, TX_START, RX_PARITY_OK, TX_PARITY_OK, \
87 RX_PARITY_ERR, TX_PARITY_ERR, RX_STOP, TX_STOP, RX_WARN, TX_WARN, \
88 RX_DATA_BIT, TX_DATA_BIT, RX_BREAK, TX_BREAK, RX_PACKET, TX_PACKET = \
92 RX, TX, RXTX = range(3)
94 class Decoder(srd.Decoder):
98 longname = 'Universal Asynchronous Receiver/Transmitter'
99 desc = 'Asynchronous, serial bus.'
103 tags = ['Embedded/industrial']
104 optional_channels = (
105 # Allow specifying only one of the signals, e.g. if only one data
106 # direction exists (or is relevant).
107 {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
108 {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
111 {'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200},
112 {'id': 'data_bits', 'desc': 'Data bits', 'default': 8,
113 'values': (5, 6, 7, 8, 9)},
114 {'id': 'parity', 'desc': 'Parity', 'default': 'none',
115 'values': ('none', 'odd', 'even', 'zero', 'one', 'ignore')},
116 {'id': 'stop_bits', 'desc': 'Stop bits', 'default': 1.0,
117 'values': (0.0, 0.5, 1.0, 1.5)},
118 {'id': 'bit_order', 'desc': 'Bit order', 'default': 'lsb-first',
119 'values': ('lsb-first', 'msb-first')},
120 {'id': 'format', 'desc': 'Data format', 'default': 'hex',
121 'values': ('ascii', 'dec', 'hex', 'oct', 'bin')},
122 {'id': 'invert_rx', 'desc': 'Invert RX', 'default': 'no',
123 'values': ('yes', 'no')},
124 {'id': 'invert_tx', 'desc': 'Invert TX', 'default': 'no',
125 'values': ('yes', 'no')},
126 {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 50},
127 {'id': 'rx_packet_delim', 'desc': 'RX packet delimiter (decimal)',
129 {'id': 'tx_packet_delim', 'desc': 'TX packet delimiter (decimal)',
131 {'id': 'rx_packet_len', 'desc': 'RX packet length', 'default': -1},
132 {'id': 'tx_packet_len', 'desc': 'TX packet length', 'default': -1},
135 ('rx-data', 'RX data'),
136 ('tx-data', 'TX data'),
137 ('rx-start', 'RX start bit'),
138 ('tx-start', 'TX start bit'),
139 ('rx-parity-ok', 'RX parity OK bit'),
140 ('tx-parity-ok', 'TX parity OK bit'),
141 ('rx-parity-err', 'RX parity error bit'),
142 ('tx-parity-err', 'TX parity error bit'),
143 ('rx-stop', 'RX stop bit'),
144 ('tx-stop', 'TX stop bit'),
145 ('rx-warning', 'RX warning'),
146 ('tx-warning', 'TX warning'),
147 ('rx-data-bit', 'RX data bit'),
148 ('tx-data-bit', 'TX data bit'),
149 ('rx-break', 'RX break'),
150 ('tx-break', 'TX break'),
151 ('rx-packet', 'RX packet'),
152 ('tx-packet', 'TX packet'),
155 ('rx-data-bits', 'RX bits', (Ann.RX_DATA_BIT,)),
156 ('rx-data-vals', 'RX data', (Ann.RX_DATA, Ann.RX_START, Ann.RX_PARITY_OK, Ann.RX_PARITY_ERR, Ann.RX_STOP)),
157 ('rx-warnings', 'RX warnings', (Ann.RX_WARN,)),
158 ('rx-breaks', 'RX breaks', (Ann.RX_BREAK,)),
159 ('rx-packets', 'RX packets', (Ann.RX_PACKET,)),
160 ('tx-data-bits', 'TX bits', (Ann.TX_DATA_BIT,)),
161 ('tx-data-vals', 'TX data', (Ann.TX_DATA, Ann.TX_START, Ann.TX_PARITY_OK, Ann.TX_PARITY_ERR, Ann.TX_STOP)),
162 ('tx-warnings', 'TX warnings', (Ann.TX_WARN,)),
163 ('tx-breaks', 'TX breaks', (Ann.TX_BREAK,)),
164 ('tx-packets', 'TX packets', (Ann.TX_PACKET,)),
169 ('rxtx', 'RX/TX dump'),
171 idle_state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
173 def putx(self, rxtx, data):
174 s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
175 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data)
177 def putx_packet(self, rxtx, data):
178 s, halfbit = self.ss_packet[rxtx], self.bit_width / 2.0
179 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data)
181 def putpx(self, rxtx, data):
182 s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
183 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_python, data)
185 def putg(self, data):
186 s, halfbit = self.samplenum, self.bit_width / 2.0
187 self.put(s - floor(halfbit), s + ceil(halfbit), self.out_ann, data)
189 def putp(self, data):
190 s, halfbit = self.samplenum, self.bit_width / 2.0
191 self.put(s - floor(halfbit), s + ceil(halfbit), self.out_python, data)
193 def putgse(self, ss, es, data):
194 self.put(ss, es, self.out_ann, data)
196 def putpse(self, ss, es, data):
197 self.put(ss, es, self.out_python, data)
199 def putbin(self, rxtx, data):
200 s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
201 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_binary, data)
207 self.samplerate = None
208 self.frame_start = [-1, -1]
209 self.frame_valid = [None, None]
210 self.startbit = [-1, -1]
211 self.cur_data_bit = [0, 0]
212 self.datavalue = [0, 0]
213 self.paritybit = [-1, -1]
214 self.stopbit1 = [-1, -1]
215 self.startsample = [-1, -1]
216 self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
217 self.databits = [[], []]
218 self.break_start = [None, None]
219 self.packet_cache = [[], []]
220 self.ss_packet, self.es_packet = [None, None], [None, None]
221 self.idle_start = [None, None]
224 self.out_python = self.register(srd.OUTPUT_PYTHON)
225 self.out_binary = self.register(srd.OUTPUT_BINARY)
226 self.out_ann = self.register(srd.OUTPUT_ANN)
227 self.bw = (self.options['data_bits'] + 7) // 8
229 def metadata(self, key, value):
230 if key == srd.SRD_CONF_SAMPLERATE:
231 self.samplerate = value
232 # The width of one UART bit in number of samples.
233 self.bit_width = float(self.samplerate) / float(self.options['baudrate'])
235 def get_sample_point(self, rxtx, bitnum):
236 # Determine absolute sample number of a bit slot's sample point.
237 # Counts for UART bits start from 0 (0 = start bit, 1..x = data,
238 # x+1 = parity bit (if used) or the first stop bit, and so on).
239 # Accept a position in the range of 1-99% of the full bit width.
240 # Assume 50% for invalid input specs for backwards compatibility.
241 perc = self.options['sample_point'] or 50
242 if not perc or perc not in range(1, 100):
245 bitpos = (self.bit_width - 1) * perc
246 bitpos += self.frame_start[rxtx]
247 bitpos += bitnum * self.bit_width
250 def wait_for_start_bit(self, rxtx, signal):
251 # Save the sample number where the start bit begins.
252 self.frame_start[rxtx] = self.samplenum
253 self.frame_valid[rxtx] = True
255 self.advance_state(rxtx, signal)
257 def get_start_bit(self, rxtx, signal):
258 self.startbit[rxtx] = signal
260 # The startbit must be 0. If not, we report an error and wait
261 # for the next start bit (assuming this one was spurious).
262 if self.startbit[rxtx] != 0:
263 self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]])
264 self.putg([Ann.RX_WARN + rxtx, ['Frame error', 'Frame err', 'FE']])
265 self.frame_valid[rxtx] = False
266 es = self.samplenum + ceil(self.bit_width / 2.0)
267 self.putpse(self.frame_start[rxtx], es, ['FRAME', rxtx,
268 (self.datavalue[rxtx], self.frame_valid[rxtx])])
269 self.advance_state(rxtx, signal, fatal = True, idle = es)
272 self.cur_data_bit[rxtx] = 0
273 self.datavalue[rxtx] = 0
274 self.startsample[rxtx] = -1
276 self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
277 self.putg([Ann.RX_START + rxtx, ['Start bit', 'Start', 'S']])
279 self.advance_state(rxtx, signal)
281 def handle_packet(self, rxtx):
282 d = 'rx' if (rxtx == RX) else 'tx'
283 delim = self.options[d + '_packet_delim']
284 plen = self.options[d + '_packet_len']
285 if delim == -1 and plen == -1:
288 # Cache data values until we see the delimiter and/or the specified
289 # packet length has been reached (whichever happens first).
290 if len(self.packet_cache[rxtx]) == 0:
291 self.ss_packet[rxtx] = self.startsample[rxtx]
292 self.packet_cache[rxtx].append(self.datavalue[rxtx])
293 if self.datavalue[rxtx] == delim or len(self.packet_cache[rxtx]) == plen:
294 self.es_packet[rxtx] = self.samplenum
296 for b in self.packet_cache[rxtx]:
297 s += self.format_value(b)
298 if self.options['format'] != 'ascii':
300 if self.options['format'] != 'ascii' and s[-1] == ' ':
301 s = s[:-1] # Drop trailing space.
302 self.putx_packet(rxtx, [Ann.RX_PACKET + rxtx, [s]])
303 self.packet_cache[rxtx] = []
305 def get_data_bits(self, rxtx, signal):
306 # Save the sample number of the middle of the first data bit.
307 if self.startsample[rxtx] == -1:
308 self.startsample[rxtx] = self.samplenum
310 self.putg([Ann.RX_DATA_BIT + rxtx, ['%d' % signal]])
312 # Store individual data bits and their start/end samplenumbers.
313 s, halfbit = self.samplenum, int(self.bit_width / 2)
314 self.databits[rxtx].append([signal, s - halfbit, s + halfbit])
316 # Return here, unless we already received all data bits.
317 self.cur_data_bit[rxtx] += 1
318 if self.cur_data_bit[rxtx] < self.options['data_bits']:
321 # Convert accumulated data bits to a data value.
322 bits = [b[0] for b in self.databits[rxtx]]
323 if self.options['bit_order'] == 'msb-first':
325 self.datavalue[rxtx] = bitpack(bits)
326 self.putpx(rxtx, ['DATA', rxtx,
327 (self.datavalue[rxtx], self.databits[rxtx])])
329 b = self.datavalue[rxtx]
330 formatted = self.format_value(b)
331 if formatted is not None:
332 self.putx(rxtx, [rxtx, [formatted]])
334 bdata = b.to_bytes(self.bw, byteorder='big')
335 self.putbin(rxtx, [Bin.RX + rxtx, bdata])
336 self.putbin(rxtx, [Bin.RXTX, bdata])
338 self.handle_packet(rxtx)
340 self.databits[rxtx] = []
342 self.advance_state(rxtx, signal)
344 def format_value(self, v):
345 # Format value 'v' according to configured options.
346 # Reflects the user selected kind of representation, as well as
347 # the number of data bits in the UART frames.
349 fmt, bits = self.options['format'], self.options['data_bits']
351 # Assume "is printable" for values from 32 to including 126,
352 # below 32 is "control" and thus not printable, above 127 is
353 # "not ASCII" in its strict sense, 127 (DEL) is not printable,
354 # fall back to hex representation for non-printables.
356 if v in range(32, 126 + 1):
358 hexfmt = "[{:02X}]" if bits <= 8 else "[{:03X}]"
359 return hexfmt.format(v)
361 # Mere number to text conversion without prefix and padding
362 # for the "decimal" output format.
364 return "{:d}".format(v)
366 # Padding with leading zeroes for hex/oct/bin formats, but
367 # without a prefix for density -- since the format is user
368 # specified, there is no ambiguity.
370 digits = (bits + 4 - 1) // 4
373 digits = (bits + 3 - 1) // 3
380 if fmtchar is not None:
381 fmt = "{{:0{:d}{:s}}}".format(digits, fmtchar)
386 def get_parity_bit(self, rxtx, signal):
387 self.paritybit[rxtx] = signal
389 if parity_ok(self.options['parity'], self.paritybit[rxtx],
390 self.datavalue[rxtx], self.options['data_bits']):
391 self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
392 self.putg([Ann.RX_PARITY_OK + rxtx, ['Parity bit', 'Parity', 'P']])
394 # TODO: Return expected/actual parity values.
395 self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
396 self.putg([Ann.RX_PARITY_ERR + rxtx, ['Parity error', 'Parity err', 'PE']])
397 self.frame_valid[rxtx] = False
399 self.advance_state(rxtx, signal)
401 # TODO: Currently only supports 1 stop bit.
402 def get_stop_bits(self, rxtx, signal):
403 self.stopbit1[rxtx] = signal
405 # Stop bits must be 1. If not, we report an error.
406 if self.stopbit1[rxtx] != 1:
407 self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
408 self.putg([Ann.RX_WARN + rxtx, ['Frame error', 'Frame err', 'FE']])
409 self.frame_valid[rxtx] = False
411 self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
412 self.putg([Ann.RX_STOP + rxtx, ['Stop bit', 'Stop', 'T']])
414 # Postprocess the UART frame
415 self.advance_state(rxtx, signal)
417 def advance_state(self, rxtx, signal = None, fatal = False, idle = None):
418 # Advances the protocol decoder's internal state for all regular
419 # UART frame inspection. Deals with either edges, sample points,
420 # or other .wait() conditions. Also gracefully handles extreme
421 # undersampling. Each turn takes one .wait() call which in turn
422 # corresponds to at least one sample. That is why as many state
423 # transitions are done here as required within a single call.
424 frame_end = self.frame_start[rxtx] + self.frame_len_sample_count
426 # When requested by the caller, start another (potential)
427 # IDLE period after the caller specified position.
428 self.idle_start[rxtx] = idle
430 # When requested by the caller, don't advance to the next
431 # UART frame's field, but to the start of the next START bit
433 self.state[rxtx] = 'WAIT FOR START BIT'
435 # Advance to the next UART frame's field that we expect. Cope
436 # with absence of optional fields. Force scan for next IDLE
437 # after the (optional) STOP bit field, so that callers need
438 # not deal with optional field presence. Also handles the cases
439 # where the decoder navigates to edges which are not strictly
440 # a field's sampling point.
441 if self.state[rxtx] == 'WAIT FOR START BIT':
442 self.state[rxtx] = 'GET START BIT'
444 if self.state[rxtx] == 'GET START BIT':
445 self.state[rxtx] = 'GET DATA BITS'
447 if self.state[rxtx] == 'GET DATA BITS':
448 self.state[rxtx] = 'GET PARITY BIT'
449 if self.options['parity'] != 'none':
452 if self.state[rxtx] == 'GET PARITY BIT':
453 self.state[rxtx] = 'GET STOP BITS'
454 if self.options['stop_bits']:
457 if self.state[rxtx] == 'GET STOP BITS':
458 # Postprocess the previously received UART frame. Advance
459 # the read position to after the frame's last bit time. So
460 # that the start of the next START bit won't fall into the
461 # end of the previously received UART frame. This improves
462 # robustness in the presence of glitchy input data.
463 ss = self.frame_start[rxtx]
464 es = self.samplenum + ceil(self.bit_width / 2.0)
465 self.handle_frame(rxtx, ss, es)
466 self.state[rxtx] = 'WAIT FOR START BIT'
467 self.idle_start[rxtx] = frame_end
469 # Unhandled state, actually a programming error. Emit diagnostics?
470 self.state[rxtx] = 'WAIT FOR START BIT'
472 def handle_frame(self, rxtx, ss, es):
473 # Pass the complete UART frame to upper layers.
474 self.putpse(ss, es, ['FRAME', rxtx,
475 (self.datavalue[rxtx], self.frame_valid[rxtx])])
477 def handle_idle(self, rxtx, ss, es):
478 self.putpse(ss, es, ['IDLE', rxtx, 0])
480 def handle_break(self, rxtx, ss, es):
481 self.putpse(ss, es, ['BREAK', rxtx, 0])
482 self.putgse(ss, es, [Ann.RX_BREAK + rxtx,
483 ['Break condition', 'Break', 'Brk', 'B']])
484 self.state[rxtx] = 'WAIT FOR START BIT'
486 def get_wait_cond(self, rxtx, inv):
487 # Return condititions that are suitable for Decoder.wait(). Those
488 # conditions either match the falling edge of the START bit, or
489 # the sample point of the next bit time.
490 state = self.state[rxtx]
491 if state == 'WAIT FOR START BIT':
492 return {rxtx: 'r' if inv else 'f'}
493 if state == 'GET START BIT':
495 elif state == 'GET DATA BITS':
496 bitnum = 1 + self.cur_data_bit[rxtx]
497 elif state == 'GET PARITY BIT':
498 bitnum = 1 + self.options['data_bits']
499 elif state == 'GET STOP BITS':
500 bitnum = 1 + self.options['data_bits']
501 bitnum += 0 if self.options['parity'] == 'none' else 1
502 want_num = ceil(self.get_sample_point(rxtx, bitnum))
503 return {'skip': want_num - self.samplenum}
505 def get_idle_cond(self, rxtx, inv):
506 # Return a condition that corresponds to the (expected) end of
507 # the next frame, assuming that it will be an "idle frame"
508 # (constant high input level for the frame's length).
509 if self.idle_start[rxtx] is None:
511 end_of_frame = self.idle_start[rxtx] + self.frame_len_sample_count
512 if end_of_frame < self.samplenum:
514 return {'skip': end_of_frame - self.samplenum}
516 def inspect_sample(self, rxtx, signal, inv):
517 # Inspect a sample returned by .wait() for the specified UART line.
521 state = self.state[rxtx]
522 if state == 'WAIT FOR START BIT':
523 self.wait_for_start_bit(rxtx, signal)
524 elif state == 'GET START BIT':
525 self.get_start_bit(rxtx, signal)
526 elif state == 'GET DATA BITS':
527 self.get_data_bits(rxtx, signal)
528 elif state == 'GET PARITY BIT':
529 self.get_parity_bit(rxtx, signal)
530 elif state == 'GET STOP BITS':
531 self.get_stop_bits(rxtx, signal)
533 def inspect_edge(self, rxtx, signal, inv):
534 # Inspect edges, independently from traffic, to detect break conditions.
538 # Signal went low. Start another interval.
539 self.break_start[rxtx] = self.samplenum
541 # Signal went high. Was there an extended period with low signal?
542 if self.break_start[rxtx] is None:
544 diff = self.samplenum - self.break_start[rxtx]
545 if diff >= self.break_min_sample_count:
546 ss, es = self.frame_start[rxtx], self.samplenum
547 self.handle_break(rxtx, ss, es)
548 self.break_start[rxtx] = None
550 def inspect_idle(self, rxtx, signal, inv):
551 # Check each edge and each period of stable input (either level).
552 # Can derive the "idle frame period has passed" condition.
556 # Low input, cease inspection.
557 self.idle_start[rxtx] = None
559 # High input, either just reached, or still stable.
560 if self.idle_start[rxtx] is None:
561 self.idle_start[rxtx] = self.samplenum
562 diff = self.samplenum - self.idle_start[rxtx]
563 if diff < self.frame_len_sample_count:
565 ss, es = self.idle_start[rxtx], self.samplenum
566 self.handle_idle(rxtx, ss, es)
567 self.idle_start[rxtx] = es
570 if not self.samplerate:
571 raise SamplerateError('Cannot decode without samplerate.')
573 has_pin = [self.has_channel(ch) for ch in (RX, TX)]
574 if not True in has_pin:
575 raise ChannelError('Need at least one of TX or RX pins.')
578 inv = [opt['invert_rx'] == 'yes', opt['invert_tx'] == 'yes']
579 cond_data_idx = [None] * len(has_pin)
581 # Determine the number of samples for a complete frame's time span.
582 # A period of low signal (at least) that long is a break condition.
583 frame_samples = 1 # START
584 frame_samples += self.options['data_bits']
585 frame_samples += 0 if self.options['parity'] == 'none' else 1
586 frame_samples += self.options['stop_bits']
587 frame_samples *= self.bit_width
588 self.frame_len_sample_count = ceil(frame_samples)
589 self.break_min_sample_count = self.frame_len_sample_count
590 cond_edge_idx = [None] * len(has_pin)
591 cond_idle_idx = [None] * len(has_pin)
596 cond_data_idx[RX] = len(conds)
597 conds.append(self.get_wait_cond(RX, inv[RX]))
598 cond_edge_idx[RX] = len(conds)
599 conds.append({RX: 'e'})
600 cond_idle_idx[RX] = None
601 idle_cond = self.get_idle_cond(RX, inv[RX])
603 cond_idle_idx[RX] = len(conds)
604 conds.append(idle_cond)
606 cond_data_idx[TX] = len(conds)
607 conds.append(self.get_wait_cond(TX, inv[TX]))
608 cond_edge_idx[TX] = len(conds)
609 conds.append({TX: 'e'})
610 cond_idle_idx[TX] = None
611 idle_cond = self.get_idle_cond(TX, inv[TX])
613 cond_idle_idx[TX] = len(conds)
614 conds.append(idle_cond)
615 (rx, tx) = self.wait(conds)
616 if cond_data_idx[RX] is not None and self.matched[cond_data_idx[RX]]:
617 self.inspect_sample(RX, rx, inv[RX])
618 if cond_edge_idx[RX] is not None and self.matched[cond_edge_idx[RX]]:
619 self.inspect_edge(RX, rx, inv[RX])
620 self.inspect_idle(RX, rx, inv[RX])
621 if cond_idle_idx[RX] is not None and self.matched[cond_idle_idx[RX]]:
622 self.inspect_idle(RX, rx, inv[RX])
623 if cond_data_idx[TX] is not None and self.matched[cond_data_idx[TX]]:
624 self.inspect_sample(TX, tx, inv[TX])
625 if cond_edge_idx[TX] is not None and self.matched[cond_edge_idx[TX]]:
626 self.inspect_edge(TX, tx, inv[TX])
627 self.inspect_idle(TX, tx, inv[TX])
628 if cond_idle_idx[TX] is not None and self.matched[cond_idle_idx[TX]]:
629 self.inspect_idle(TX, tx, inv[TX])