2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
30 class Decoder(srd.Decoder):
34 longname = 'Texas Instruments TLC5620'
35 desc = 'Texas Instruments TLC5620 8-bit quad DAC.'
40 {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'},
41 {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'},
44 {'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'},
45 {'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'},
48 ('dac-select', 'DAC select'),
50 ('value', 'DAC value'),
51 ('data-latch', 'Data latch point'),
52 ('ldac-fall', 'LDAC falling edge'),
54 ('operation', 'Operation'),
57 ('bits', 'Bits', (5,)),
58 ('fields', 'Fields', (0, 1, 2)),
59 ('operations', 'Operations', (6,)),
60 ('events', 'Events', (3, 4)),
63 def __init__(self, **kwargs):
64 self.oldpins = self.oldclk = self.oldload = self.oldldac = None
67 self.ss_dac = self.es_dac = 0
68 self.ss_gain = self.es_gain = 0
69 self.ss_value = self.es_value = 0
70 self.dac_select = self.gain = self.dac_value = None
73 self.out_ann = self.register(srd.OUTPUT_ANN)
75 def handle_11bits(self):
76 # Only look at the last 11 bits, the rest is ignored by the TLC5620.
77 if len(self.bits) > 11:
78 self.bits = self.bits[-11:]
80 self.ss_dac = self.bits[0][1]
81 self.es_dac = self.ss_gain = self.bits[2][1]
82 self.es_gain = self.ss_value = self.bits[3][1]
83 self.clock_width = self.es_gain - self.ss_gain
84 self.es_value = self.bits[10][1] + self.clock_width # Guessed.
86 s = ''.join(str(i[0]) for i in self.bits[:2])
87 self.dac_select = s = dacs[int(s, 2)]
88 self.put(self.ss_dac, self.es_dac, self.out_ann,
89 [0, ['DAC select: %s' % s, 'DAC sel: %s' % s,
90 'DAC: %s' % s, 'D: %s' % s, s, s[3]]])
92 self.gain = g = 1 + self.bits[2][0]
93 self.put(self.ss_gain, self.es_gain, self.out_ann,
94 [1, ['Gain: x%d' % g, 'G: x%d' % g, 'x%d' % g]])
96 s = ''.join(str(i[0]) for i in self.bits[3:])
97 self.dac_value = v = int(s, 2)
98 self.put(self.ss_value, self.es_value, self.out_ann,
99 [2, ['DAC value: %d' % v, 'Value: %d' % v, 'Val: %d' % v,
100 'V: %d' % v, '%d' % v]])
102 # Emit an annotation for each bit.
103 for i in range(1, 11):
104 self.put(self.bits[i - 1][1], self.bits[i][1], self.out_ann,
105 [5, [str(self.bits[i - 1][0])]])
106 self.put(self.bits[10][1], self.bits[10][1] + self.clock_width,
107 self.out_ann, [5, [str(self.bits[10][0])]])
111 def handle_falling_edge_load(self):
113 s, v, g = self.dac_select, self.dac_value, self.gain
114 self.put(self.samplenum, self.samplenum, self.out_ann,
115 [3, ['Falling edge on LOAD', 'LOAD fall', 'F']])
116 self.put(self.ss_dac, self.es_value, self.out_ann,
117 [6, ['Setting %s value to %d (x%d gain)' % (s, v, g),
118 '%s=%d (x%d gain)' % (s, v, g)]])
120 def handle_falling_edge_ldac(self):
121 self.put(self.samplenum, self.samplenum, self.out_ann,
122 [4, ['Falling edge on LDAC', 'LDAC fall', 'LDAC', 'L']])
124 def handle_new_dac_bit(self):
125 self.bits.append([self.datapin, self.samplenum])
127 def decode(self, ss, es, data):
128 for (self.samplenum, pins) in data:
130 # Ignore identical samples early on (for performance reasons).
131 if self.oldpins == pins:
133 self.oldpins, (clk, self.datapin, load, ldac) = pins, pins
135 # DATA is shifted in the DAC on the falling CLK edge (MSB-first).
136 # A falling edge of LOAD will latch the data.
138 if self.oldload == 1 and load == 0:
139 self.handle_falling_edge_load()
140 if self.oldldac == 1 and ldac == 0:
141 self.handle_falling_edge_ldac()
142 if self.oldclk == 1 and clk == 0:
143 self.handle_new_dac_bit()