2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 import sigrokdecode as srd
25 Protocol output format:
28 [<cmd>, <data1>, <data2>]
31 - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
32 The data is _usually_ 8 bits (but can also be fewer or more bits).
33 Both data items are Python numbers, not strings.
34 - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
35 Both data items are Python numbers (0/1), not strings.
44 # Key: (CPOL, CPHA). Value: SPI mode.
45 # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
46 # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
54 class Decoder(srd.Decoder):
58 longname = 'Serial Peripheral Interface'
59 desc = 'Full-duplex, synchronous, serial bus.'
64 {'id': 'miso', 'name': 'MISO',
65 'desc': 'SPI MISO line (Master in, slave out)'},
66 {'id': 'mosi', 'name': 'MOSI',
67 'desc': 'SPI MOSI line (Master out, slave in)'},
68 {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
71 {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'},
74 'cs_polarity': ['CS# polarity', 'active-low'],
75 'cpol': ['Clock polarity', 0],
76 'cpha': ['Clock phase', 0],
77 'bitorder': ['Bit order within the SPI data', 'msb-first'],
78 'wordsize': ['Word size of SPI data', 8], # 1-64?
79 'format': ['Data format', 'hex'],
82 ['miso-mosi-data', 'MISO/MOSI SPI data'],
83 ['miso-data', 'MISO SPI data'],
84 ['mosi-data', 'MOSI SPI data'],
85 ['warnings', 'Human-readable warnings'],
89 self.samplerate = None
96 self.cs_was_deasserted_during_data_word = 0
101 def metadata(self, key, value):
102 if key == srd.SRD_CONF_SAMPLERATE:
103 self.samplerate = value
106 self.out_proto = self.register(srd.OUTPUT_PYTHON)
107 self.out_ann = self.register(srd.OUTPUT_ANN)
108 self.out_bitrate = self.register(srd.OUTPUT_META,
109 meta=(int, 'Bitrate', 'Bitrate during transfers'))
111 def putpw(self, data):
112 self.put(self.startsample, self.samplenum, self.out_proto, data)
114 def putw(self, data):
115 self.put(self.startsample, self.samplenum, self.out_ann, data)
117 def handle_bit(self, miso, mosi, sck, cs):
118 # If this is the first bit, save its sample number.
119 if self.bitcount == 0:
120 self.startsample = self.samplenum
122 active_low = (self.options['cs_polarity'] == 'active-low')
123 deasserted = cs if active_low else not cs
125 self.cs_was_deasserted_during_data_word = 1
127 ws = self.options['wordsize']
129 # Receive MOSI bit into our shift register.
130 if self.options['bitorder'] == 'msb-first':
131 self.mosidata |= mosi << (ws - 1 - self.bitcount)
133 self.mosidata |= mosi << self.bitcount
135 # Receive MISO bit into our shift register.
136 if self.options['bitorder'] == 'msb-first':
137 self.misodata |= miso << (ws - 1 - self.bitcount)
139 self.misodata |= miso << self.bitcount
143 # Continue to receive if not enough bits were received, yet.
144 if self.bitcount != ws:
147 # Pass MOSI and MISO to the next PD up the stack
148 self.putpw(['DATA', self.mosidata, self.misodata])
151 self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]])
152 self.putw([1, ['%02X' % self.misodata]])
153 self.putw([2, ['%02X' % self.mosidata]])
156 elapsed = 1 / float(self.samplerate) * (self.samplenum - self.startsample + 1)
157 bitrate = int(1 / elapsed * self.options['wordsize'])
158 self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)
160 if self.cs_was_deasserted_during_data_word:
161 self.putw([3, ['CS# was deasserted during this data word!']])
163 # Reset decoder state.
164 self.mosidata = self.misodata = self.bitcount = 0
166 def find_clk_edge(self, miso, mosi, sck, cs):
167 if self.have_cs and self.oldcs != cs:
168 # Send all CS# pin value changes.
169 self.put(self.samplenum, self.samplenum, self.out_proto,
170 ['CS-CHANGE', self.oldcs, cs])
172 # Reset decoder state when CS# changes (and the CS# pin is used).
173 self.mosidata = self.misodata = self.bitcount= 0
175 # Ignore sample if the clock pin hasn't changed.
176 if sck == self.oldsck:
181 # Sample data on rising/falling clock edge (depends on mode).
182 mode = spi_mode[self.options['cpol'], self.options['cpha']]
183 if mode == 0 and sck == 0: # Sample on rising clock edge
185 elif mode == 1 and sck == 1: # Sample on falling clock edge
187 elif mode == 2 and sck == 1: # Sample on falling clock edge
189 elif mode == 3 and sck == 0: # Sample on rising clock edge
192 # Found the correct clock edge, now get the SPI bit(s).
193 self.handle_bit(miso, mosi, sck, cs)
195 def decode(self, ss, es, data):
196 if self.samplerate is None:
197 raise Exception("Cannot decode without samplerate.")
198 # TODO: Either MISO or MOSI could be optional. CS# is optional.
199 for (self.samplenum, pins) in data:
201 # Ignore identical samples early on (for performance reasons).
202 if self.oldpins == pins:
204 self.oldpins, (miso, mosi, sck, cs) = pins, pins
205 self.have_cs = (cs in (0, 1))
208 if self.state == 'IDLE':
209 self.find_clk_edge(miso, mosi, sck, cs)
211 raise Exception('Invalid state: %s' % self.state)