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Commit | Line | Data |
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6eb87578 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
6eb87578 GM |
3 | ## |
4 | ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> | |
3eda7779 | 5 | ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de> |
6eb87578 GM |
6 | ## |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
18 | ## along with this program; if not, write to the Free Software | |
19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | ## | |
ad2dc0de | 21 | |
156509ca UH |
22 | # SPI protocol decoder |
23 | ||
677d597b | 24 | import sigrokdecode as srd |
67e847fd | 25 | |
8a7ce2a3 | 26 | # Key: (CPOL, CPHA). Value: SPI mode. |
94bbdb9a UH |
27 | # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive. |
28 | # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge. | |
c94c8c91 UH |
29 | spi_mode = { |
30 | (0, 0): 0, # Mode 0 | |
31 | (0, 1): 1, # Mode 1 | |
32 | (1, 0): 2, # Mode 2 | |
33 | (1, 1): 3, # Mode 3 | |
34 | } | |
35 | ||
677d597b | 36 | class Decoder(srd.Decoder): |
a2c2afd9 | 37 | api_version = 1 |
67e847fd | 38 | id = 'spi' |
2b7d0e2b | 39 | name = 'SPI' |
3d3da57d | 40 | longname = 'Serial Peripheral Interface' |
a465436e | 41 | desc = 'Full-duplex, synchronous, serial bus.' |
6eb87578 GM |
42 | license = 'gplv2+' |
43 | inputs = ['logic'] | |
44 | outputs = ['spi'] | |
6b5b91d2 | 45 | probes = [ |
4e570fa9 UH |
46 | {'id': 'miso', 'name': 'MISO', |
47 | 'desc': 'SPI MISO line (Master in, slave out)'}, | |
decde15e UH |
48 | {'id': 'mosi', 'name': 'MOSI', |
49 | 'desc': 'SPI MOSI line (Master out, slave in)'}, | |
6b5b91d2 UH |
50 | {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, |
51 | ] | |
efa64173 UH |
52 | optional_probes = [ |
53 | {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'}, | |
54 | ] | |
238b4080 | 55 | options = { |
94bbdb9a UH |
56 | 'cs_polarity': ['CS# polarity', 'active-low'], |
57 | 'cpol': ['Clock polarity', 0], | |
58 | 'cpha': ['Clock phase', 0], | |
59 | 'bitorder': ['Bit order within the SPI data', 'msb-first'], | |
c94c8c91 | 60 | 'wordsize': ['Word size of SPI data', 8], # 1-64? |
3eda7779 | 61 | 'format': ['Data format', 'hex'], |
238b4080 | 62 | } |
b1bb5eed | 63 | annotations = [ |
29f8bb7b UH |
64 | ['MISO/MOSI data', 'MISO/MOSI SPI data'], |
65 | ['MISO data', 'MISO SPI data'], | |
66 | ['MOSI data', 'MOSI SPI data'], | |
3eda7779 | 67 | ['Warnings', 'Human-readable warnings'], |
b1bb5eed | 68 | ] |
6eb87578 | 69 | |
3643fc3f | 70 | def __init__(self): |
c66baa8c | 71 | self.oldsck = 1 |
a10bfc48 | 72 | self.bitcount = 0 |
4917bb31 | 73 | self.mosidata = 0 |
d6bace96 | 74 | self.misodata = 0 |
6eb87578 | 75 | self.bytesreceived = 0 |
ec0afe27 | 76 | self.startsample = -1 |
d6bace96 | 77 | self.samplenum = -1 |
01329e88 | 78 | self.cs_was_deasserted_during_data_word = 0 |
3e3c0330 | 79 | self.oldcs = -1 |
2fcd7c22 | 80 | self.oldpins = None |
191ec8c5 | 81 | self.state = 'IDLE' |
6eb87578 | 82 | |
3643fc3f | 83 | def start(self, metadata): |
d6bace96 | 84 | self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') |
56202222 | 85 | self.out_ann = self.add(srd.OUTPUT_ANN, 'spi') |
3643fc3f | 86 | |
6eb87578 | 87 | def report(self): |
e100d51e | 88 | return 'SPI: %d bytes received' % self.bytesreceived |
6eb87578 | 89 | |
ec0afe27 UH |
90 | def putpw(self, data): |
91 | self.put(self.startsample, self.samplenum, self.out_proto, data) | |
92 | ||
93 | def putw(self, data): | |
94 | self.put(self.startsample, self.samplenum, self.out_ann, data) | |
95 | ||
191ec8c5 UH |
96 | def handle_bit(self, miso, mosi, sck, cs): |
97 | # If this is the first bit, save its sample number. | |
98 | if self.bitcount == 0: | |
99 | self.startsample = self.samplenum | |
efa64173 UH |
100 | if self.have_cs: |
101 | active_low = (self.options['cs_polarity'] == 'active-low') | |
102 | deasserted = cs if active_low else not cs | |
103 | if deasserted: | |
104 | self.cs_was_deasserted_during_data_word = 1 | |
2fcd7c22 | 105 | |
191ec8c5 | 106 | ws = self.options['wordsize'] |
d6bace96 | 107 | |
191ec8c5 UH |
108 | # Receive MOSI bit into our shift register. |
109 | if self.options['bitorder'] == 'msb-first': | |
110 | self.mosidata |= mosi << (ws - 1 - self.bitcount) | |
111 | else: | |
112 | self.mosidata |= mosi << self.bitcount | |
3e3c0330 | 113 | |
191ec8c5 UH |
114 | # Receive MISO bit into our shift register. |
115 | if self.options['bitorder'] == 'msb-first': | |
116 | self.misodata |= miso << (ws - 1 - self.bitcount) | |
117 | else: | |
118 | self.misodata |= miso << self.bitcount | |
c94c8c91 | 119 | |
191ec8c5 | 120 | self.bitcount += 1 |
1ea831e9 | 121 | |
191ec8c5 UH |
122 | # Continue to receive if not enough bits were received, yet. |
123 | if self.bitcount != ws: | |
124 | return | |
b1bb5eed | 125 | |
191ec8c5 UH |
126 | self.putpw(['DATA', self.mosidata, self.misodata]) |
127 | self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]]) | |
128 | self.putw([1, ['%02X' % self.misodata]]) | |
129 | self.putw([2, ['%02X' % self.mosidata]]) | |
b1bb5eed | 130 | |
191ec8c5 UH |
131 | if self.cs_was_deasserted_during_data_word: |
132 | self.putw([3, ['CS# was deasserted during this data word!']]) | |
133 | ||
134 | # Reset decoder state. | |
efa64173 | 135 | self.mosidata = self.misodata = self.bitcount = 0 |
191ec8c5 UH |
136 | |
137 | # Keep stats for summary. | |
138 | self.bytesreceived += 1 | |
139 | ||
140 | def find_clk_edge(self, miso, mosi, sck, cs): | |
efa64173 | 141 | if self.have_cs and self.oldcs != cs: |
191ec8c5 UH |
142 | # Send all CS# pin value changes. |
143 | self.put(self.samplenum, self.samplenum, self.out_proto, | |
144 | ['CS-CHANGE', self.oldcs, cs]) | |
145 | self.oldcs = cs | |
efa64173 UH |
146 | # Reset decoder state when CS# changes (and the CS# pin is used). |
147 | self.mosidata = self.misodata = self.bitcount= 0 | |
191ec8c5 UH |
148 | |
149 | # Ignore sample if the clock pin hasn't changed. | |
150 | if sck == self.oldsck: | |
151 | return | |
b1bb5eed | 152 | |
191ec8c5 | 153 | self.oldsck = sck |
b1bb5eed | 154 | |
191ec8c5 UH |
155 | # Sample data on rising/falling clock edge (depends on mode). |
156 | mode = spi_mode[self.options['cpol'], self.options['cpha']] | |
157 | if mode == 0 and sck == 0: # Sample on rising clock edge | |
158 | return | |
159 | elif mode == 1 and sck == 1: # Sample on falling clock edge | |
160 | return | |
161 | elif mode == 2 and sck == 1: # Sample on falling clock edge | |
162 | return | |
163 | elif mode == 3 and sck == 0: # Sample on rising clock edge | |
164 | return | |
165 | ||
166 | # Found the correct clock edge, now get the SPI bit(s). | |
167 | self.handle_bit(miso, mosi, sck, cs) | |
168 | ||
169 | def decode(self, ss, es, data): | |
170 | # TODO: Either MISO or MOSI could be optional. CS# is optional. | |
171 | for (self.samplenum, pins) in data: | |
01329e88 | 172 | |
191ec8c5 UH |
173 | # Ignore identical samples early on (for performance reasons). |
174 | if self.oldpins == pins: | |
175 | continue | |
176 | self.oldpins, (miso, mosi, sck, cs) = pins, pins | |
efa64173 | 177 | self.have_cs = (cs in (0, 1)) |
b1bb5eed | 178 | |
191ec8c5 UH |
179 | # State machine. |
180 | if self.state == 'IDLE': | |
181 | self.find_clk_edge(miso, mosi, sck, cs) | |
182 | else: | |
183 | raise Exception('Invalid state: %s' % self.state) | |
ad2dc0de | 184 |