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Commit | Line | Data |
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6eb87578 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
6eb87578 GM |
3 | ## |
4 | ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> | |
3eda7779 | 5 | ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de> |
6eb87578 GM |
6 | ## |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
18 | ## along with this program; if not, write to the Free Software | |
19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | ## | |
ad2dc0de | 21 | |
156509ca UH |
22 | # SPI protocol decoder |
23 | ||
677d597b | 24 | import sigrokdecode as srd |
67e847fd | 25 | |
8a7ce2a3 | 26 | # Key: (CPOL, CPHA). Value: SPI mode. |
94bbdb9a UH |
27 | # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive. |
28 | # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge. | |
c94c8c91 UH |
29 | spi_mode = { |
30 | (0, 0): 0, # Mode 0 | |
31 | (0, 1): 1, # Mode 1 | |
32 | (1, 0): 2, # Mode 2 | |
33 | (1, 1): 3, # Mode 3 | |
34 | } | |
35 | ||
677d597b | 36 | class Decoder(srd.Decoder): |
a2c2afd9 | 37 | api_version = 1 |
67e847fd | 38 | id = 'spi' |
2b7d0e2b | 39 | name = 'SPI' |
3d3da57d | 40 | longname = 'Serial Peripheral Interface' |
a465436e | 41 | desc = 'Full-duplex, synchronous, serial bus.' |
6eb87578 GM |
42 | license = 'gplv2+' |
43 | inputs = ['logic'] | |
44 | outputs = ['spi'] | |
6b5b91d2 | 45 | probes = [ |
4e570fa9 UH |
46 | {'id': 'miso', 'name': 'MISO', |
47 | 'desc': 'SPI MISO line (Master in, slave out)'}, | |
decde15e UH |
48 | {'id': 'mosi', 'name': 'MOSI', |
49 | 'desc': 'SPI MOSI line (Master out, slave in)'}, | |
6b5b91d2 | 50 | {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, |
4e570fa9 | 51 | {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'}, |
6b5b91d2 | 52 | ] |
b77614bc | 53 | optional_probes = [] # TODO |
238b4080 | 54 | options = { |
94bbdb9a UH |
55 | 'cs_polarity': ['CS# polarity', 'active-low'], |
56 | 'cpol': ['Clock polarity', 0], | |
57 | 'cpha': ['Clock phase', 0], | |
58 | 'bitorder': ['Bit order within the SPI data', 'msb-first'], | |
c94c8c91 | 59 | 'wordsize': ['Word size of SPI data', 8], # 1-64? |
3eda7779 | 60 | 'format': ['Data format', 'hex'], |
238b4080 | 61 | } |
b1bb5eed | 62 | annotations = [ |
29f8bb7b UH |
63 | ['MISO/MOSI data', 'MISO/MOSI SPI data'], |
64 | ['MISO data', 'MISO SPI data'], | |
65 | ['MOSI data', 'MOSI SPI data'], | |
3eda7779 | 66 | ['Warnings', 'Human-readable warnings'], |
b1bb5eed | 67 | ] |
6eb87578 | 68 | |
3643fc3f | 69 | def __init__(self): |
c66baa8c | 70 | self.oldsck = 1 |
a10bfc48 | 71 | self.bitcount = 0 |
4917bb31 | 72 | self.mosidata = 0 |
d6bace96 | 73 | self.misodata = 0 |
6eb87578 | 74 | self.bytesreceived = 0 |
ec0afe27 | 75 | self.startsample = -1 |
d6bace96 | 76 | self.samplenum = -1 |
01329e88 | 77 | self.cs_was_deasserted_during_data_word = 0 |
3e3c0330 | 78 | self.oldcs = -1 |
2fcd7c22 | 79 | self.oldpins = None |
6eb87578 | 80 | |
3643fc3f | 81 | def start(self, metadata): |
d6bace96 | 82 | self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') |
56202222 | 83 | self.out_ann = self.add(srd.OUTPUT_ANN, 'spi') |
3643fc3f | 84 | |
6eb87578 | 85 | def report(self): |
e100d51e | 86 | return 'SPI: %d bytes received' % self.bytesreceived |
6eb87578 | 87 | |
ec0afe27 UH |
88 | def putpw(self, data): |
89 | self.put(self.startsample, self.samplenum, self.out_proto, data) | |
90 | ||
91 | def putw(self, data): | |
92 | self.put(self.startsample, self.samplenum, self.out_ann, data) | |
93 | ||
2b9837d9 | 94 | def decode(self, ss, es, data): |
decde15e | 95 | # TODO: Either MISO or MOSI could be optional. CS# is optional. |
2fcd7c22 UH |
96 | for (self.samplenum, pins) in data: |
97 | ||
98 | # Ignore identical samples early on (for performance reasons). | |
99 | if self.oldpins == pins: | |
100 | continue | |
101 | self.oldpins, (miso, mosi, sck, cs) = pins, pins | |
d6bace96 | 102 | |
3e3c0330 UH |
103 | if self.oldcs != cs: |
104 | # Send all CS# pin value changes. | |
105 | self.put(self.samplenum, self.samplenum, self.out_proto, | |
106 | ['CS-CHANGE', self.oldcs, cs]) | |
3e3c0330 UH |
107 | self.oldcs = cs |
108 | ||
c94c8c91 | 109 | # Ignore sample if the clock pin hasn't changed. |
6eb87578 GM |
110 | if sck == self.oldsck: |
111 | continue | |
c94c8c91 | 112 | |
6eb87578 | 113 | self.oldsck = sck |
c94c8c91 UH |
114 | |
115 | # Sample data on rising/falling clock edge (depends on mode). | |
8a7ce2a3 | 116 | mode = spi_mode[self.options['cpol'], self.options['cpha']] |
c94c8c91 UH |
117 | if mode == 0 and sck == 0: # Sample on rising clock edge |
118 | continue | |
119 | elif mode == 1 and sck == 1: # Sample on falling clock edge | |
120 | continue | |
121 | elif mode == 2 and sck == 1: # Sample on falling clock edge | |
122 | continue | |
123 | elif mode == 3 and sck == 0: # Sample on rising clock edge | |
124 | continue | |
6eb87578 | 125 | |
d6bace96 | 126 | # If this is the first bit, save its sample number. |
a10bfc48 | 127 | if self.bitcount == 0: |
ec0afe27 | 128 | self.startsample = self.samplenum |
94bbdb9a | 129 | active_low = (self.options['cs_polarity'] == 'active-low') |
8a7ce2a3 | 130 | deasserted = cs if active_low else not cs |
acba4869 | 131 | if deasserted: |
01329e88 | 132 | self.cs_was_deasserted_during_data_word = 1 |
b1bb5eed | 133 | |
fd4aa8aa UH |
134 | ws = self.options['wordsize'] |
135 | ||
1ea831e9 | 136 | # Receive MOSI bit into our shift register. |
94bbdb9a | 137 | if self.options['bitorder'] == 'msb-first': |
fd4aa8aa | 138 | self.mosidata |= mosi << (ws - 1 - self.bitcount) |
1ea831e9 UH |
139 | else: |
140 | self.mosidata |= mosi << self.bitcount | |
141 | ||
142 | # Receive MISO bit into our shift register. | |
94bbdb9a | 143 | if self.options['bitorder'] == 'msb-first': |
fd4aa8aa | 144 | self.misodata |= miso << (ws - 1 - self.bitcount) |
1ea831e9 UH |
145 | else: |
146 | self.misodata |= miso << self.bitcount | |
b1bb5eed | 147 | |
a10bfc48 | 148 | self.bitcount += 1 |
b1bb5eed | 149 | |
fd4aa8aa UH |
150 | # Continue to receive if not enough bits were received, yet. |
151 | if self.bitcount != ws: | |
6eb87578 | 152 | continue |
b1bb5eed | 153 | |
ec0afe27 | 154 | self.putpw(['DATA', self.mosidata, self.misodata]) |
29f8bb7b UH |
155 | self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]]) |
156 | self.putw([1, ['%02X' % self.misodata]]) | |
157 | self.putw([2, ['%02X' % self.mosidata]]) | |
b1bb5eed | 158 | |
01329e88 | 159 | if self.cs_was_deasserted_during_data_word: |
29f8bb7b | 160 | self.putw([3, ['CS# was deasserted during this data word!']]) |
01329e88 | 161 | |
b1bb5eed | 162 | # Reset decoder state. |
4917bb31 | 163 | self.mosidata = 0 |
d6bace96 | 164 | self.misodata = 0 |
a10bfc48 | 165 | self.bitcount = 0 |
b1bb5eed UH |
166 | |
167 | # Keep stats for summary. | |
6eb87578 | 168 | self.bytesreceived += 1 |
ad2dc0de | 169 |