[libsigrokdecode.git] / decoders / jtag / jtag.py

##
## This file is part of the sigrok project.
##
## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

# JTAG protocol decoder

import sigrokdecode as srd

class Decoder(srd.Decoder):
    api_version = 1
    id = 'jtag'
    name = 'JTAG'
    longname = 'Joint Test Action Group'
    desc = 'TODO.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['jtag']
    probes = [
        {'id': 'tdi',  'name': 'TDI',  'desc': 'Test data input'},
        {'id': 'tdo',  'name': 'TDO',  'desc': 'Test data output'},
        {'id': 'tck',  'name': 'TCK',  'desc': 'Test clock'},
        {'id': 'tms',  'name': 'TMS',  'desc': 'Test mode select'},
        {'id': 'trst', 'name': 'TRST', 'desc': 'Test reset'},
    ]
    optional_probes = [] # TODO? SRST?
    options = {}
    annotations = [
        ['ASCII', 'TODO: description'],
    ]

    def __init__(self, **kwargs):
        self.state = 'TEST-LOGIC-RESET'
        self.oldpins = (-1, -1, -1, -1, -1)
        self.oldtck = -1
        self.bits_tdi = []
        self.bits_tdo = []

    def start(self, metadata):
        self.out_proto = self.add(srd.OUTPUT_PROTO, 'jtag')
        self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag')

    def report(self):
        pass

    def advance_state_machine(self, tms):
        # Intro "tree"
        if self.state == 'TEST-LOGIC-RESET':
            self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
        elif self.state == 'RUN-TEST/IDLE':
            self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'

        # DR "tree"
        elif self.state == 'SELECT-DR-SCAN':
            self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
        elif self.state == 'CAPTURE-DR':
            self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
        elif self.state == 'SHIFT-DR':
            self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
        elif self.state == 'EXIT1-DR':
            self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
        elif self.state == 'PAUSE-DR':
            self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
        elif self.state == 'EXIT2-DR':
            self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
        elif self.state == 'UPDATE-DR':
            self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'

        # IR "tree"
        elif self.state == 'SELECT-IR-SCAN':
            self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
        elif self.state == 'CAPTURE-IR':
            self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
        elif self.state == 'SHIFT-IR':
            self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
        elif self.state == 'EXIT1-IR':
            self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
        elif self.state == 'PAUSE-IR':
            self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
        elif self.state == 'EXIT2-IR':
            self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
        elif self.state == 'UPDATE-IR':
            self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'

        else:
            raise Exception('Invalid state: %s' % self.state)

    def handle_rising_tck_edge(self, tdi, tdo, tck, tms, trst):
        # In SHIFT-DR/SHIFT-IR (on rising TCK edges) we collect TDI values.
        if self.state in ('SHIFT-DR', 'SHIFT-IR'):
            self.bits_tdi.append(tdi)

        # Output all TDI bits.
        elif self.state in ('EXIT1-DR', 'EXIT1-IR'):
            s = self.state[-2:] + ' TDI: ' + ''.join(map(str, self.bits_tdi))
            s += ', ' + str(len(self.bits_tdi)) + ' bits'
            self.put(self.ss, self.es, self.out_ann, [0, [s]])
            self.bits_tdi = []

        # Rising TCK edges always advance the state machine.
        self.advance_state_machine(tms)

        # Output the state we just switched to.
        self.put(self.ss, self.es, self.out_ann,
                 [0, ['New state: %s' % self.state]])

    def handle_falling_tck_edge(self, tdi, tdo, tck, tms, trst):
        # In SHIFT-DR/SHIFT-IR (on falling TCK edges) we collect TDO values.
        if self.state in ('SHIFT-DR', 'SHIFT-IR'):
            self.bits_tdo.append(tdo)

        # Output all TDO bits.
        if self.state in ('EXIT1-DR', 'EXIT1-IR'):
            s = self.state[-2:] + ' TDO: ' + ''.join(map(str, self.bits_tdo))
            s += ', ' + str(len(self.bits_tdo)) + ' bits'
            self.put(self.ss, self.es, self.out_ann, [0, [s]])
            self.bits_tdo = []

    def decode(self, ss, es, data):
        for (samplenum, pins) in data:

            # If none of the pins changed, there's nothing to do.
            if self.oldpins == pins:
                continue

            # Store current pin values for the next round.
            self.oldpins = pins

            # Get individual pin values into local variables.
            # TODO: Handle optional pins.
            (tdi, tdo, tck, tms, trst) = pins

            # We only care about TCK edges (either rising or falling).
            if (self.oldtck == tck):
                continue

            # Store start/end sample for later usage.
            self.ss, self.es = ss, es

            if (self.oldtck == 0 and tck == 1):
                self.handle_rising_tck_edge(tdi, tdo, tck, tms, trst)
            elif (self.oldtck == 1 and tck == 0):
                self.handle_falling_tck_edge(tdi, tdo, tck, tms, trst)

            self.oldtck = tck
Commit	Line	Data
557a143d UH	1	##
	2	## This file is part of the sigrok project.
	3	##
	4	## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	# JTAG protocol decoder
	22
	23	import sigrokdecode as srd
	24
	25	class Decoder(srd.Decoder):
	26	api_version = 1
	27	id = 'jtag'
	28	name = 'JTAG'
	29	longname = 'Joint Test Action Group'
	30	desc = 'TODO.'
	31	license = 'gplv2+'
	32	inputs = ['logic']
	33	outputs = ['jtag']
	34	probes = [
	35	{'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'},
	36	{'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'},
	37	{'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'},
	38	{'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'},
	39	{'id': 'trst', 'name': 'TRST', 'desc': 'Test reset'},
	40	]
	41	optional_probes = [] # TODO? SRST?
	42	options = {}
	43	annotations = [
	44	['ASCII', 'TODO: description'],
	45	]
	46
	47	def __init__(self, **kwargs):
	48	self.state = 'TEST-LOGIC-RESET'
	49	self.oldpins = (-1, -1, -1, -1, -1)
	50	self.oldtck = -1
	51	self.bits_tdi = []
	52	self.bits_tdo = []
	53
	54	def start(self, metadata):
	55	self.out_proto = self.add(srd.OUTPUT_PROTO, 'jtag')
	56	self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag')
	57
	58	def report(self):
	59	pass
	60
	61	def advance_state_machine(self, tms):
	62	# Intro "tree"
	63	if self.state == 'TEST-LOGIC-RESET':
	64	self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
65	elif self.state == 'RUN-TEST/IDLE':
66	self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
67
68	# DR "tree"
69	elif self.state == 'SELECT-DR-SCAN':
70	self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
71	elif self.state == 'CAPTURE-DR':
72	self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
73	elif self.state == 'SHIFT-DR':
74	self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
75	elif self.state == 'EXIT1-DR':
76	self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
77	elif self.state == 'PAUSE-DR':
78	self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
79	elif self.state == 'EXIT2-DR':
80	self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
81	elif self.state == 'UPDATE-DR':
82	self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
83
84	# IR "tree"
85	elif self.state == 'SELECT-IR-SCAN':
86	self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
87	elif self.state == 'CAPTURE-IR':
88	self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
89	elif self.state == 'SHIFT-IR':
90	self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
91	elif self.state == 'EXIT1-IR':
92	self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
93	elif self.state == 'PAUSE-IR':
94	self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
95	elif self.state == 'EXIT2-IR':
96	self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
97	elif self.state == 'UPDATE-IR':
98	self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
99
100	else:
101	raise Exception('Invalid state: %s' % self.state)
102
103	def handle_rising_tck_edge(self, tdi, tdo, tck, tms, trst):
104	# In SHIFT-DR/SHIFT-IR (on rising TCK edges) we collect TDI values.
105	if self.state in ('SHIFT-DR', 'SHIFT-IR'):
106	self.bits_tdi.append(tdi)
107
108	# Output all TDI bits.
109	elif self.state in ('EXIT1-DR', 'EXIT1-IR'):
110	s = self.state[-2:] + ' TDI: ' + ''.join(map(str, self.bits_tdi))
111	s += ', ' + str(len(self.bits_tdi)) + ' bits'
112	self.put(self.ss, self.es, self.out_ann, [0, [s]])
113	self.bits_tdi = []
114
115	# Rising TCK edges always advance the state machine.
116	self.advance_state_machine(tms)
117
118	# Output the state we just switched to.
119	self.put(self.ss, self.es, self.out_ann,
120	[0, ['New state: %s' % self.state]])
121
122	def handle_falling_tck_edge(self, tdi, tdo, tck, tms, trst):
123	# In SHIFT-DR/SHIFT-IR (on falling TCK edges) we collect TDO values.
124	if self.state in ('SHIFT-DR', 'SHIFT-IR'):
125	self.bits_tdo.append(tdo)
126
127	# Output all TDO bits.
128	if self.state in ('EXIT1-DR', 'EXIT1-IR'):
129	s = self.state[-2:] + ' TDO: ' + ''.join(map(str, self.bits_tdo))
130	s += ', ' + str(len(self.bits_tdo)) + ' bits'
131	self.put(self.ss, self.es, self.out_ann, [0, [s]])
132	self.bits_tdo = []
133
134	def decode(self, ss, es, data):
135	for (samplenum, pins) in data:
136
137	# If none of the pins changed, there's nothing to do.
138	if self.oldpins == pins:
139	continue
140
141	# Store current pin values for the next round.
142	self.oldpins = pins
143
144	# Get individual pin values into local variables.
145	# TODO: Handle optional pins.
146	(tdi, tdo, tck, tms, trst) = pins
147
148	# We only care about TCK edges (either rising or falling).
149	if (self.oldtck == tck):
150	continue
151
152	# Store start/end sample for later usage.
153	self.ss, self.es = ss, es
154
155	if (self.oldtck == 0 and tck == 1):
156	self.handle_rising_tck_edge(tdi, tdo, tck, tms, trst)
157	elif (self.oldtck == 1 and tck == 0):
158	self.handle_falling_tck_edge(tdi, tdo, tck, tms, trst)
159
160	self.oldtck = tck
161