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Commit | Line | Data |
---|---|---|
28a35d8a | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
28a35d8a | 3 | * |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
45c59c8b BV |
30 | #include "libsigrok.h" |
31 | #include "libsigrok-internal.h" | |
28a35d8a HE |
32 | #include "asix-sigma.h" |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
c50277a6 | 39 | #define TRIGGER_TYPE "rf10" |
28a35d8a | 40 | |
ed300b9f | 41 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; |
a873c594 | 42 | static struct sr_dev_driver *di = &asix_sigma_driver_info; |
6078d2c9 | 43 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data); |
28a35d8a | 44 | |
b1648dea MV |
45 | /* |
46 | * The ASIX Sigma supports arbitrary integer frequency divider in | |
47 | * the 50MHz mode. The divider is in range 1...256 , allowing for | |
48 | * very precise sampling rate selection. This driver supports only | |
49 | * a subset of the sampling rates. | |
50 | */ | |
2c9c0df8 | 51 | static const uint64_t samplerates[] = { |
b1648dea MV |
52 | SR_KHZ(200), /* div=250 */ |
53 | SR_KHZ(250), /* div=200 */ | |
54 | SR_KHZ(500), /* div=100 */ | |
55 | SR_MHZ(1), /* div=50 */ | |
56 | SR_MHZ(5), /* div=10 */ | |
57 | SR_MHZ(10), /* div=5 */ | |
58 | SR_MHZ(25), /* div=2 */ | |
59 | SR_MHZ(50), /* div=1 */ | |
60 | SR_MHZ(100), /* Special FW needed */ | |
61 | SR_MHZ(200), /* Special FW needed */ | |
28a35d8a HE |
62 | }; |
63 | ||
d261dbbf | 64 | /* |
ba7dd8bb | 65 | * Channel numbers seem to go from 1-16, according to this image: |
d261dbbf UH |
66 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg |
67 | * (the cable has two additional GND pins, and a TI and TO pin) | |
68 | */ | |
790c7ccc | 69 | static const char *channel_names[] = { |
78693401 UH |
70 | "1", "2", "3", "4", "5", "6", "7", "8", |
71 | "9", "10", "11", "12", "13", "14", "15", "16", | |
464d12c7 KS |
72 | }; |
73 | ||
2c9c0df8 | 74 | static const int32_t hwcaps[] = { |
1953564a BV |
75 | SR_CONF_LOGIC_ANALYZER, |
76 | SR_CONF_SAMPLERATE, | |
38d32464 | 77 | SR_CONF_TRIGGER_TYPE, |
1953564a | 78 | SR_CONF_CAPTURE_RATIO, |
1953564a | 79 | SR_CONF_LIMIT_MSEC, |
6868626b | 80 | SR_CONF_LIMIT_SAMPLES, |
28a35d8a HE |
81 | }; |
82 | ||
fefa1800 UH |
83 | /* Initialize the logic analyzer mode. */ |
84 | static uint8_t logic_mode_start[] = { | |
85 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
86 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
87 | }; | |
88 | ||
499b17e9 MV |
89 | static const char *sigma_firmware_files[] = { |
90 | /* 50 MHz, supports 8 bit fractions */ | |
91 | FIRMWARE_DIR "/asix-sigma-50.fw", | |
92 | /* 100 MHz */ | |
93 | FIRMWARE_DIR "/asix-sigma-100.fw", | |
94 | /* 200 MHz */ | |
95 | FIRMWARE_DIR "/asix-sigma-200.fw", | |
96 | /* Synchronous clock from pin */ | |
97 | FIRMWARE_DIR "/asix-sigma-50sync.fw", | |
98 | /* Frequency counter */ | |
99 | FIRMWARE_DIR "/asix-sigma-phasor.fw", | |
f6564c8d HE |
100 | }; |
101 | ||
0e1357e8 | 102 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
103 | { |
104 | int ret; | |
fefa1800 | 105 | |
0e1357e8 | 106 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 107 | if (ret < 0) { |
47f4f073 | 108 | sr_err("ftdi_read_data failed: %s", |
0e1357e8 | 109 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
110 | } |
111 | ||
112 | return ret; | |
113 | } | |
114 | ||
0e1357e8 | 115 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
116 | { |
117 | int ret; | |
fefa1800 | 118 | |
0e1357e8 | 119 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 120 | if (ret < 0) { |
47f4f073 | 121 | sr_err("ftdi_write_data failed: %s", |
0e1357e8 | 122 | ftdi_get_error_string(&devc->ftdic)); |
fefa1800 | 123 | } else if ((size_t) ret != size) { |
47f4f073 | 124 | sr_err("ftdi_write_data did not complete write."); |
28a35d8a HE |
125 | } |
126 | ||
127 | return ret; | |
128 | } | |
129 | ||
99965709 | 130 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 131 | struct dev_context *devc) |
28a35d8a HE |
132 | { |
133 | size_t i; | |
134 | uint8_t buf[len + 2]; | |
135 | int idx = 0; | |
136 | ||
137 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
138 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
139 | ||
fefa1800 | 140 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
141 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
142 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
143 | } | |
144 | ||
0e1357e8 | 145 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
146 | } |
147 | ||
0e1357e8 | 148 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 149 | { |
0e1357e8 | 150 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
151 | } |
152 | ||
99965709 | 153 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 154 | struct dev_context *devc) |
28a35d8a HE |
155 | { |
156 | uint8_t buf[3]; | |
fefa1800 | 157 | |
28a35d8a HE |
158 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
159 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
160 | buf[2] = REG_READ_ADDR; |
161 | ||
0e1357e8 | 162 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 163 | |
0e1357e8 | 164 | return sigma_read(data, len, devc); |
28a35d8a HE |
165 | } |
166 | ||
0e1357e8 | 167 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) |
28a35d8a HE |
168 | { |
169 | uint8_t value; | |
fefa1800 | 170 | |
0e1357e8 | 171 | if (1 != sigma_read_register(reg, &value, 1, devc)) { |
47f4f073 | 172 | sr_err("sigma_get_register: 1 byte expected"); |
28a35d8a HE |
173 | return 0; |
174 | } | |
175 | ||
176 | return value; | |
177 | } | |
178 | ||
99965709 | 179 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 180 | struct dev_context *devc) |
28a35d8a HE |
181 | { |
182 | uint8_t buf[] = { | |
183 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
184 | ||
185 | REG_READ_ADDR | NEXT_REG, | |
186 | REG_READ_ADDR | NEXT_REG, | |
187 | REG_READ_ADDR | NEXT_REG, | |
188 | REG_READ_ADDR | NEXT_REG, | |
189 | REG_READ_ADDR | NEXT_REG, | |
190 | REG_READ_ADDR | NEXT_REG, | |
191 | }; | |
28a35d8a HE |
192 | uint8_t result[6]; |
193 | ||
0e1357e8 | 194 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 195 | |
0e1357e8 | 196 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
197 | |
198 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
199 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
200 | ||
57bbf56b HE |
201 | /* Not really sure why this must be done, but according to spec. */ |
202 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
203 | stoppos -= 64; | |
204 | ||
205 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
206 | triggerpos -= 64; | |
207 | ||
28a35d8a HE |
208 | return 1; |
209 | } | |
210 | ||
99965709 | 211 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 212 | uint8_t *data, struct dev_context *devc) |
28a35d8a HE |
213 | { |
214 | size_t i; | |
215 | uint8_t buf[4096]; | |
216 | int idx = 0; | |
217 | ||
fefa1800 | 218 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
219 | buf[0] = startchunk >> 8; |
220 | buf[1] = startchunk & 0xff; | |
0e1357e8 | 221 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); |
28a35d8a | 222 | |
fefa1800 | 223 | /* Read the DRAM. */ |
28a35d8a HE |
224 | buf[idx++] = REG_DRAM_BLOCK; |
225 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
226 | ||
227 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
228 | /* Alternate bit to copy from DRAM to cache. */ |
229 | if (i != (numchunks - 1)) | |
230 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
231 | |
232 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
233 | ||
fefa1800 | 234 | if (i != (numchunks - 1)) |
28a35d8a HE |
235 | buf[idx++] = REG_DRAM_WAIT_ACK; |
236 | } | |
237 | ||
0e1357e8 | 238 | sigma_write(buf, idx, devc); |
28a35d8a | 239 | |
0e1357e8 | 240 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); |
28a35d8a HE |
241 | } |
242 | ||
4ae1f451 | 243 | /* Upload trigger look-up tables to Sigma. */ |
0e1357e8 | 244 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
245 | { |
246 | int i; | |
247 | uint8_t tmp[2]; | |
248 | uint16_t bit; | |
249 | ||
250 | /* Transpose the table and send to Sigma. */ | |
251 | for (i = 0; i < 16; ++i) { | |
252 | bit = 1 << i; | |
253 | ||
254 | tmp[0] = tmp[1] = 0; | |
255 | ||
256 | if (lut->m2d[0] & bit) | |
257 | tmp[0] |= 0x01; | |
258 | if (lut->m2d[1] & bit) | |
259 | tmp[0] |= 0x02; | |
260 | if (lut->m2d[2] & bit) | |
261 | tmp[0] |= 0x04; | |
262 | if (lut->m2d[3] & bit) | |
263 | tmp[0] |= 0x08; | |
264 | ||
265 | if (lut->m3 & bit) | |
266 | tmp[0] |= 0x10; | |
267 | if (lut->m3s & bit) | |
268 | tmp[0] |= 0x20; | |
269 | if (lut->m4 & bit) | |
270 | tmp[0] |= 0x40; | |
271 | ||
272 | if (lut->m0d[0] & bit) | |
273 | tmp[1] |= 0x01; | |
274 | if (lut->m0d[1] & bit) | |
275 | tmp[1] |= 0x02; | |
276 | if (lut->m0d[2] & bit) | |
277 | tmp[1] |= 0x04; | |
278 | if (lut->m0d[3] & bit) | |
279 | tmp[1] |= 0x08; | |
280 | ||
281 | if (lut->m1d[0] & bit) | |
282 | tmp[1] |= 0x10; | |
283 | if (lut->m1d[1] & bit) | |
284 | tmp[1] |= 0x20; | |
285 | if (lut->m1d[2] & bit) | |
286 | tmp[1] |= 0x40; | |
287 | if (lut->m1d[3] & bit) | |
288 | tmp[1] |= 0x80; | |
289 | ||
99965709 | 290 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
0e1357e8 BV |
291 | devc); |
292 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
ee492173 HE |
293 | } |
294 | ||
295 | /* Send the parameters */ | |
296 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
0e1357e8 | 297 | sizeof(lut->params), devc); |
ee492173 | 298 | |
e46b8fb1 | 299 | return SR_OK; |
ee492173 HE |
300 | } |
301 | ||
fefa1800 | 302 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 303 | static int bin2bitbang(const char *filename, |
fefa1800 | 304 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 305 | { |
fefa1800 | 306 | FILE *f; |
e3fff420 | 307 | unsigned long file_size; |
28a35d8a HE |
308 | unsigned long offset = 0; |
309 | unsigned char *p; | |
e3fff420 HE |
310 | uint8_t *firmware; |
311 | unsigned long fwsize = 0; | |
28a35d8a HE |
312 | const int buffer_size = 65536; |
313 | size_t i; | |
e3fff420 | 314 | int c, bit, v; |
fefa1800 | 315 | uint32_t imm = 0x3f6df2ab; |
28a35d8a | 316 | |
868d8cef | 317 | f = g_fopen(filename, "rb"); |
28a35d8a | 318 | if (!f) { |
47f4f073 | 319 | sr_err("g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 320 | return SR_ERR; |
28a35d8a HE |
321 | } |
322 | ||
323 | if (-1 == fseek(f, 0, SEEK_END)) { | |
47f4f073 | 324 | sr_err("fseek on %s failed", filename); |
28a35d8a | 325 | fclose(f); |
b53738ba | 326 | return SR_ERR; |
28a35d8a HE |
327 | } |
328 | ||
329 | file_size = ftell(f); | |
330 | ||
331 | fseek(f, 0, SEEK_SET); | |
332 | ||
b53738ba | 333 | if (!(firmware = g_try_malloc(buffer_size))) { |
47f4f073 | 334 | sr_err("%s: firmware malloc failed", __func__); |
12ad53f5 | 335 | fclose(f); |
b53738ba | 336 | return SR_ERR_MALLOC; |
28a35d8a HE |
337 | } |
338 | ||
28a35d8a HE |
339 | while ((c = getc(f)) != EOF) { |
340 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
e3fff420 | 341 | firmware[fwsize++] = c ^ imm; |
28a35d8a HE |
342 | } |
343 | fclose(f); | |
344 | ||
e3fff420 | 345 | if(fwsize != file_size) { |
47f4f073 | 346 | sr_err("%s: Error reading firmware", filename); |
e3fff420 HE |
347 | fclose(f); |
348 | g_free(firmware); | |
349 | return SR_ERR; | |
28a35d8a HE |
350 | } |
351 | ||
28a35d8a HE |
352 | *buf_size = fwsize * 2 * 8; |
353 | ||
b53738ba | 354 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 355 | if (!p) { |
47f4f073 | 356 | sr_err("%s: buf/p malloc failed", __func__); |
12ad53f5 | 357 | g_free(firmware); |
b53738ba | 358 | return SR_ERR_MALLOC; |
28a35d8a HE |
359 | } |
360 | ||
361 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 362 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 363 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
364 | p[offset++] = v | 0x01; |
365 | p[offset++] = v; | |
366 | } | |
367 | } | |
368 | ||
369 | g_free(firmware); | |
370 | ||
371 | if (offset != *buf_size) { | |
372 | g_free(*buf); | |
47f4f073 | 373 | sr_err("Error reading firmware %s " |
0aeb0ccd | 374 | "offset=%ld, file_size=%ld, buf_size=%zd.", |
133a37bf | 375 | filename, offset, file_size, *buf_size); |
28a35d8a | 376 | |
b53738ba | 377 | return SR_ERR; |
28a35d8a HE |
378 | } |
379 | ||
b53738ba | 380 | return SR_OK; |
28a35d8a HE |
381 | } |
382 | ||
3678cf73 | 383 | static void clear_helper(void *priv) |
0448d110 | 384 | { |
0e1357e8 | 385 | struct dev_context *devc; |
ce4d26dd | 386 | |
3678cf73 | 387 | devc = priv; |
0e1357e8 | 388 | |
3678cf73 UH |
389 | ftdi_deinit(&devc->ftdic); |
390 | } | |
0448d110 | 391 | |
3b412e3a | 392 | static int dev_clear(void) |
3678cf73 UH |
393 | { |
394 | return std_dev_clear(di, clear_helper); | |
0448d110 BV |
395 | } |
396 | ||
6078d2c9 | 397 | static int init(struct sr_context *sr_ctx) |
61136ea6 | 398 | { |
f6beaac5 | 399 | return std_init(sr_ctx, di, LOG_PREFIX); |
61136ea6 BV |
400 | } |
401 | ||
6078d2c9 | 402 | static GSList *scan(GSList *options) |
28a35d8a | 403 | { |
d68e2d1a | 404 | struct sr_dev_inst *sdi; |
ba7dd8bb | 405 | struct sr_channel *ch; |
0e1357e8 BV |
406 | struct drv_context *drvc; |
407 | struct dev_context *devc; | |
0448d110 | 408 | GSList *devices; |
e3fff420 HE |
409 | struct ftdi_device_list *devlist; |
410 | char serial_txt[10]; | |
411 | uint32_t serial; | |
790c7ccc MV |
412 | int ret; |
413 | unsigned int i; | |
28a35d8a | 414 | |
0448d110 | 415 | (void)options; |
64d33dc2 | 416 | |
a873c594 | 417 | drvc = di->priv; |
4b97c74e | 418 | |
0448d110 | 419 | devices = NULL; |
4b97c74e | 420 | |
0e1357e8 | 421 | if (!(devc = g_try_malloc(sizeof(struct dev_context)))) { |
47f4f073 | 422 | sr_err("%s: devc malloc failed", __func__); |
0448d110 | 423 | return NULL; |
b53738ba | 424 | } |
99965709 | 425 | |
0e1357e8 | 426 | ftdi_init(&devc->ftdic); |
28a35d8a | 427 | |
fefa1800 | 428 | /* Look for SIGMAs. */ |
e3fff420 | 429 | |
0e1357e8 | 430 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, |
eec944c5 BV |
431 | USB_VENDOR, USB_PRODUCT)) <= 0) { |
432 | if (ret < 0) | |
433 | sr_err("ftdi_usb_find_all(): %d", ret); | |
99965709 | 434 | goto free; |
eec944c5 | 435 | } |
99965709 | 436 | |
e3fff420 | 437 | /* Make sure it's a version 1 or 2 SIGMA. */ |
0e1357e8 | 438 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, |
6352d030 | 439 | serial_txt, sizeof(serial_txt)); |
e3fff420 HE |
440 | sscanf(serial_txt, "%x", &serial); |
441 | ||
6352d030 | 442 | if (serial < 0xa6010000 || serial > 0xa602ffff) { |
47f4f073 UH |
443 | sr_err("Only SIGMA and SIGMA2 are supported " |
444 | "in this version of libsigrok."); | |
e3fff420 HE |
445 | goto free; |
446 | } | |
447 | ||
448 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
449 | ||
0e1357e8 BV |
450 | devc->cur_samplerate = 0; |
451 | devc->period_ps = 0; | |
452 | devc->limit_msec = 0; | |
453 | devc->cur_firmware = -1; | |
ba7dd8bb | 454 | devc->num_channels = 0; |
0e1357e8 BV |
455 | devc->samples_per_event = 0; |
456 | devc->capture_ratio = 50; | |
457 | devc->use_triggers = 0; | |
28a35d8a | 458 | |
fefa1800 | 459 | /* Register SIGMA device. */ |
d68e2d1a | 460 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
55f98c65 | 461 | USB_MODEL_NAME, NULL))) { |
47f4f073 | 462 | sr_err("%s: sdi was NULL", __func__); |
99965709 | 463 | goto free; |
d68e2d1a | 464 | } |
a873c594 | 465 | sdi->driver = di; |
87ca93c5 | 466 | |
790c7ccc MV |
467 | for (i = 0; i < ARRAY_SIZE(channel_names); i++) { |
468 | ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE, | |
469 | channel_names[i]); | |
470 | if (!ch) | |
87ca93c5 | 471 | return NULL; |
ba7dd8bb | 472 | sdi->channels = g_slist_append(sdi->channels, ch); |
87ca93c5 BV |
473 | } |
474 | ||
0448d110 | 475 | devices = g_slist_append(devices, sdi); |
0e1357e8 BV |
476 | drvc->instances = g_slist_append(drvc->instances, sdi); |
477 | sdi->priv = devc; | |
28a35d8a | 478 | |
fefa1800 | 479 | /* We will open the device again when we need it. */ |
e3fff420 | 480 | ftdi_list_free(&devlist); |
28a35d8a | 481 | |
0448d110 | 482 | return devices; |
ea9cfed7 | 483 | |
99965709 | 484 | free: |
0e1357e8 BV |
485 | ftdi_deinit(&devc->ftdic); |
486 | g_free(devc); | |
0448d110 | 487 | return NULL; |
28a35d8a HE |
488 | } |
489 | ||
6078d2c9 | 490 | static GSList *dev_list(void) |
811deee4 | 491 | { |
0e94d524 | 492 | return ((struct drv_context *)(di->priv))->instances; |
811deee4 BV |
493 | } |
494 | ||
d5fa188a MV |
495 | /* |
496 | * Configure the FPGA for bitbang mode. | |
497 | * This sequence is documented in section 2. of the ASIX Sigma programming | |
498 | * manual. This sequence is necessary to configure the FPGA in the Sigma | |
499 | * into Bitbang mode, in which it can be programmed with the firmware. | |
500 | */ | |
501 | static int sigma_fpga_init_bitbang(struct dev_context *devc) | |
502 | { | |
503 | uint8_t suicide[] = { | |
504 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
505 | }; | |
506 | uint8_t init_array[] = { | |
507 | 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, | |
508 | 0x01, 0x01, | |
509 | }; | |
510 | int i, ret, timeout = 10000; | |
511 | uint8_t data; | |
512 | ||
513 | /* Section 2. part 1), do the FPGA suicide. */ | |
514 | sigma_write(suicide, sizeof(suicide), devc); | |
515 | sigma_write(suicide, sizeof(suicide), devc); | |
516 | sigma_write(suicide, sizeof(suicide), devc); | |
517 | sigma_write(suicide, sizeof(suicide), devc); | |
518 | ||
519 | /* Section 2. part 2), do pulse on D1. */ | |
520 | sigma_write(init_array, sizeof(init_array), devc); | |
521 | ftdi_usb_purge_buffers(&devc->ftdic); | |
522 | ||
523 | /* Wait until the FPGA asserts D6/INIT_B. */ | |
524 | for (i = 0; i < timeout; i++) { | |
525 | ret = sigma_read(&data, 1, devc); | |
526 | if (ret < 0) | |
527 | return ret; | |
528 | /* Test if pin D6 got asserted. */ | |
529 | if (data & (1 << 5)) | |
530 | return 0; | |
531 | /* The D6 was not asserted yet, wait a bit. */ | |
532 | usleep(10000); | |
533 | } | |
534 | ||
535 | return SR_ERR_TIMEOUT; | |
536 | } | |
537 | ||
0e1357e8 | 538 | static int upload_firmware(int firmware_idx, struct dev_context *devc) |
28a35d8a HE |
539 | { |
540 | int ret; | |
541 | unsigned char *buf; | |
542 | unsigned char pins; | |
543 | size_t buf_size; | |
28a35d8a | 544 | unsigned char result[32]; |
499b17e9 | 545 | const char *firmware = sigma_firmware_files[firmware_idx]; |
8bbf7627 | 546 | struct ftdi_context *ftdic = &devc->ftdic; |
28a35d8a | 547 | |
fefa1800 | 548 | /* Make sure it's an ASIX SIGMA. */ |
8bbf7627 MV |
549 | ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT, |
550 | USB_DESCRIPTION, NULL); | |
551 | if (ret < 0) { | |
47f4f073 | 552 | sr_err("ftdi_usb_open failed: %s", |
8bbf7627 | 553 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
554 | return 0; |
555 | } | |
556 | ||
8bbf7627 MV |
557 | ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG); |
558 | if (ret < 0) { | |
47f4f073 | 559 | sr_err("ftdi_set_bitmode failed: %s", |
8bbf7627 | 560 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
561 | return 0; |
562 | } | |
563 | ||
fefa1800 | 564 | /* Four times the speed of sigmalogan - Works well. */ |
8bbf7627 MV |
565 | ret = ftdi_set_baudrate(ftdic, 750000); |
566 | if (ret < 0) { | |
47f4f073 | 567 | sr_err("ftdi_set_baudrate failed: %s", |
8bbf7627 | 568 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
569 | return 0; |
570 | } | |
571 | ||
d5fa188a MV |
572 | /* Initialize the FPGA for firmware upload. */ |
573 | ret = sigma_fpga_init_bitbang(devc); | |
574 | if (ret) | |
575 | return ret; | |
28a35d8a | 576 | |
9ddb2a12 | 577 | /* Prepare firmware. */ |
8bbf7627 MV |
578 | ret = bin2bitbang(firmware, &buf, &buf_size); |
579 | if (ret != SR_OK) { | |
47f4f073 | 580 | sr_err("An error occured while reading the firmware: %s", |
499b17e9 | 581 | firmware); |
b53738ba | 582 | return ret; |
28a35d8a HE |
583 | } |
584 | ||
fefa1800 | 585 | /* Upload firmare. */ |
499b17e9 | 586 | sr_info("Uploading firmware file '%s'.", firmware); |
0e1357e8 | 587 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
588 | |
589 | g_free(buf); | |
590 | ||
8bbf7627 MV |
591 | ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET); |
592 | if (ret < 0) { | |
47f4f073 | 593 | sr_err("ftdi_set_bitmode failed: %s", |
8bbf7627 | 594 | ftdi_get_error_string(ftdic)); |
e46b8fb1 | 595 | return SR_ERR; |
28a35d8a HE |
596 | } |
597 | ||
8bbf7627 | 598 | ftdi_usb_purge_buffers(ftdic); |
28a35d8a | 599 | |
fefa1800 | 600 | /* Discard garbage. */ |
0e1357e8 | 601 | while (1 == sigma_read(&pins, 1, devc)) |
28a35d8a HE |
602 | ; |
603 | ||
fefa1800 | 604 | /* Initialize the logic analyzer mode. */ |
0e1357e8 | 605 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); |
28a35d8a | 606 | |
fefa1800 | 607 | /* Expect a 3 byte reply. */ |
0e1357e8 | 608 | ret = sigma_read(result, 3, devc); |
28a35d8a HE |
609 | if (ret != 3 || |
610 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
47f4f073 | 611 | sr_err("Configuration failed. Invalid reply received."); |
e46b8fb1 | 612 | return SR_ERR; |
28a35d8a HE |
613 | } |
614 | ||
0e1357e8 | 615 | devc->cur_firmware = firmware_idx; |
f6564c8d | 616 | |
47f4f073 | 617 | sr_info("Firmware uploaded."); |
e3fff420 | 618 | |
e46b8fb1 | 619 | return SR_OK; |
f6564c8d HE |
620 | } |
621 | ||
6078d2c9 | 622 | static int dev_open(struct sr_dev_inst *sdi) |
f6564c8d | 623 | { |
0e1357e8 | 624 | struct dev_context *devc; |
f6564c8d HE |
625 | int ret; |
626 | ||
0e1357e8 | 627 | devc = sdi->priv; |
99965709 | 628 | |
9ddb2a12 | 629 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 630 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
f6564c8d HE |
631 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
632 | ||
47f4f073 | 633 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 634 | ftdi_get_error_string(&devc->ftdic)); |
f6564c8d HE |
635 | |
636 | return 0; | |
637 | } | |
28a35d8a | 638 | |
5a2326a7 | 639 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 640 | |
e46b8fb1 | 641 | return SR_OK; |
f6564c8d HE |
642 | } |
643 | ||
6f4b1868 | 644 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 645 | { |
2c9c0df8 BV |
646 | struct dev_context *devc; |
647 | unsigned int i; | |
648 | int ret; | |
f6564c8d | 649 | |
2c9c0df8 | 650 | devc = sdi->priv; |
f4abaa9f UH |
651 | ret = SR_OK; |
652 | ||
2c9c0df8 BV |
653 | for (i = 0; i < ARRAY_SIZE(samplerates); i++) { |
654 | if (samplerates[i] == samplerate) | |
f6564c8d HE |
655 | break; |
656 | } | |
2c9c0df8 | 657 | if (samplerates[i] == 0) |
e46b8fb1 | 658 | return SR_ERR_SAMPLERATE; |
f6564c8d | 659 | |
59df0c77 | 660 | if (samplerate <= SR_MHZ(50)) { |
0e1357e8 | 661 | ret = upload_firmware(0, devc); |
ba7dd8bb | 662 | devc->num_channels = 16; |
e8397563 | 663 | } |
59df0c77 | 664 | if (samplerate == SR_MHZ(100)) { |
0e1357e8 | 665 | ret = upload_firmware(1, devc); |
ba7dd8bb | 666 | devc->num_channels = 8; |
f78898e9 | 667 | } |
59df0c77 | 668 | else if (samplerate == SR_MHZ(200)) { |
0e1357e8 | 669 | ret = upload_firmware(2, devc); |
ba7dd8bb | 670 | devc->num_channels = 4; |
f78898e9 | 671 | } |
f6564c8d | 672 | |
0e1357e8 | 673 | devc->cur_samplerate = samplerate; |
5edc02c7 | 674 | devc->period_ps = 1000000000000ULL / samplerate; |
ba7dd8bb | 675 | devc->samples_per_event = 16 / devc->num_channels; |
0e1357e8 | 676 | devc->state.state = SIGMA_IDLE; |
f6564c8d | 677 | |
e8397563 | 678 | return ret; |
28a35d8a HE |
679 | } |
680 | ||
c53d793f HE |
681 | /* |
682 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
683 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
ba7dd8bb | 684 | * in addition to value/mask trigger for any number of channels. |
c53d793f HE |
685 | * |
686 | * The Sigma supports complex triggers using boolean expressions, but this | |
687 | * has not been implemented yet. | |
688 | */ | |
ba7dd8bb | 689 | static int configure_channels(const struct sr_dev_inst *sdi) |
57bbf56b | 690 | { |
0e1357e8 | 691 | struct dev_context *devc = sdi->priv; |
ba7dd8bb | 692 | const struct sr_channel *ch; |
1b79df2f | 693 | const GSList *l; |
57bbf56b | 694 | int trigger_set = 0; |
ba7dd8bb | 695 | int channelbit; |
57bbf56b | 696 | |
0e1357e8 | 697 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 698 | |
ba7dd8bb UH |
699 | for (l = sdi->channels; l; l = l->next) { |
700 | ch = (struct sr_channel *)l->data; | |
701 | channelbit = 1 << (ch->index); | |
57bbf56b | 702 | |
ba7dd8bb | 703 | if (!ch->enabled || !ch->trigger) |
57bbf56b HE |
704 | continue; |
705 | ||
0e1357e8 | 706 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 707 | /* Fast trigger support. */ |
ee492173 | 708 | if (trigger_set) { |
47f4f073 UH |
709 | sr_err("Only a single pin trigger in 100 and " |
710 | "200MHz mode is supported."); | |
e46b8fb1 | 711 | return SR_ERR; |
ee492173 | 712 | } |
ba7dd8bb UH |
713 | if (ch->trigger[0] == 'f') |
714 | devc->trigger.fallingmask |= channelbit; | |
715 | else if (ch->trigger[0] == 'r') | |
716 | devc->trigger.risingmask |= channelbit; | |
ee492173 | 717 | else { |
47f4f073 UH |
718 | sr_err("Only rising/falling trigger in 100 " |
719 | "and 200MHz mode is supported."); | |
e46b8fb1 | 720 | return SR_ERR; |
ee492173 | 721 | } |
57bbf56b | 722 | |
c53d793f | 723 | ++trigger_set; |
ee492173 | 724 | } else { |
c53d793f | 725 | /* Simple trigger support (event). */ |
ba7dd8bb UH |
726 | if (ch->trigger[0] == '1') { |
727 | devc->trigger.simplevalue |= channelbit; | |
728 | devc->trigger.simplemask |= channelbit; | |
c53d793f | 729 | } |
ba7dd8bb UH |
730 | else if (ch->trigger[0] == '0') { |
731 | devc->trigger.simplevalue &= ~channelbit; | |
732 | devc->trigger.simplemask |= channelbit; | |
c53d793f | 733 | } |
ba7dd8bb UH |
734 | else if (ch->trigger[0] == 'f') { |
735 | devc->trigger.fallingmask |= channelbit; | |
c53d793f HE |
736 | ++trigger_set; |
737 | } | |
ba7dd8bb UH |
738 | else if (ch->trigger[0] == 'r') { |
739 | devc->trigger.risingmask |= channelbit; | |
c53d793f HE |
740 | ++trigger_set; |
741 | } | |
ee492173 | 742 | |
ea9cfed7 UH |
743 | /* |
744 | * Actually, Sigma supports 2 rising/falling triggers, | |
745 | * but they are ORed and the current trigger syntax | |
746 | * does not permit ORed triggers. | |
747 | */ | |
98b8cbc1 | 748 | if (trigger_set > 1) { |
47f4f073 UH |
749 | sr_err("Only 1 rising/falling trigger " |
750 | "is supported."); | |
e46b8fb1 | 751 | return SR_ERR; |
ee492173 | 752 | } |
ee492173 | 753 | } |
5b5ea7c6 HE |
754 | |
755 | if (trigger_set) | |
0e1357e8 | 756 | devc->use_triggers = 1; |
57bbf56b HE |
757 | } |
758 | ||
e46b8fb1 | 759 | return SR_OK; |
57bbf56b HE |
760 | } |
761 | ||
6078d2c9 | 762 | static int dev_close(struct sr_dev_inst *sdi) |
28a35d8a | 763 | { |
0e1357e8 | 764 | struct dev_context *devc; |
28a35d8a | 765 | |
961009b0 | 766 | devc = sdi->priv; |
697785d1 UH |
767 | |
768 | /* TODO */ | |
769 | if (sdi->status == SR_ST_ACTIVE) | |
0e1357e8 | 770 | ftdi_usb_close(&devc->ftdic); |
697785d1 UH |
771 | |
772 | sdi->status = SR_ST_INACTIVE; | |
773 | ||
774 | return SR_OK; | |
28a35d8a HE |
775 | } |
776 | ||
6078d2c9 | 777 | static int cleanup(void) |
28a35d8a | 778 | { |
3b412e3a | 779 | return dev_clear(); |
28a35d8a HE |
780 | } |
781 | ||
8f996b89 | 782 | static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi, |
53b4680f | 783 | const struct sr_channel_group *cg) |
28a35d8a | 784 | { |
0e1357e8 | 785 | struct dev_context *devc; |
99965709 | 786 | |
53b4680f | 787 | (void)cg; |
8f996b89 | 788 | |
035a1078 | 789 | switch (id) { |
123e1313 | 790 | case SR_CONF_SAMPLERATE: |
41479605 | 791 | if (sdi) { |
0e1357e8 | 792 | devc = sdi->priv; |
2c9c0df8 | 793 | *data = g_variant_new_uint64(devc->cur_samplerate); |
41479605 BV |
794 | } else |
795 | return SR_ERR; | |
28a35d8a | 796 | break; |
d7bbecfd | 797 | default: |
bd6fbf62 | 798 | return SR_ERR_NA; |
28a35d8a HE |
799 | } |
800 | ||
41479605 | 801 | return SR_OK; |
28a35d8a HE |
802 | } |
803 | ||
8f996b89 | 804 | static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi, |
53b4680f | 805 | const struct sr_channel_group *cg) |
28a35d8a | 806 | { |
0e1357e8 | 807 | struct dev_context *devc; |
6868626b | 808 | uint64_t num_samples; |
28a35d8a | 809 | int ret; |
f6564c8d | 810 | |
53b4680f | 811 | (void)cg; |
8f996b89 | 812 | |
e73ffd42 BV |
813 | if (sdi->status != SR_ST_ACTIVE) |
814 | return SR_ERR_DEV_CLOSED; | |
815 | ||
0e1357e8 | 816 | devc = sdi->priv; |
99965709 | 817 | |
6868626b BV |
818 | switch (id) { |
819 | case SR_CONF_SAMPLERATE: | |
2c9c0df8 | 820 | ret = set_samplerate(sdi, g_variant_get_uint64(data)); |
6868626b BV |
821 | break; |
822 | case SR_CONF_LIMIT_MSEC: | |
2c9c0df8 | 823 | devc->limit_msec = g_variant_get_uint64(data); |
0e1357e8 | 824 | if (devc->limit_msec > 0) |
e46b8fb1 | 825 | ret = SR_OK; |
94ba4bd6 | 826 | else |
e46b8fb1 | 827 | ret = SR_ERR; |
6868626b BV |
828 | break; |
829 | case SR_CONF_LIMIT_SAMPLES: | |
830 | num_samples = g_variant_get_uint64(data); | |
831 | devc->limit_msec = num_samples * 1000 / devc->cur_samplerate; | |
832 | break; | |
833 | case SR_CONF_CAPTURE_RATIO: | |
2c9c0df8 | 834 | devc->capture_ratio = g_variant_get_uint64(data); |
0e1357e8 | 835 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) |
e46b8fb1 | 836 | ret = SR_ERR; |
94ba4bd6 | 837 | else |
e46b8fb1 | 838 | ret = SR_OK; |
6868626b BV |
839 | break; |
840 | default: | |
bd6fbf62 | 841 | ret = SR_ERR_NA; |
28a35d8a HE |
842 | } |
843 | ||
844 | return ret; | |
845 | } | |
846 | ||
8f996b89 | 847 | static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi, |
53b4680f | 848 | const struct sr_channel_group *cg) |
a1c743fc | 849 | { |
2c9c0df8 BV |
850 | GVariant *gvar; |
851 | GVariantBuilder gvb; | |
a1c743fc BV |
852 | |
853 | (void)sdi; | |
53b4680f | 854 | (void)cg; |
a1c743fc BV |
855 | |
856 | switch (key) { | |
9a6517d1 | 857 | case SR_CONF_DEVICE_OPTIONS: |
2c9c0df8 BV |
858 | *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32, |
859 | hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t)); | |
9a6517d1 | 860 | break; |
a1c743fc | 861 | case SR_CONF_SAMPLERATE: |
2c9c0df8 BV |
862 | g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}")); |
863 | gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates, | |
864 | ARRAY_SIZE(samplerates), sizeof(uint64_t)); | |
865 | g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar); | |
866 | *data = g_variant_builder_end(&gvb); | |
a1c743fc | 867 | break; |
c50277a6 | 868 | case SR_CONF_TRIGGER_TYPE: |
2c9c0df8 | 869 | *data = g_variant_new_string(TRIGGER_TYPE); |
c50277a6 | 870 | break; |
a1c743fc | 871 | default: |
bd6fbf62 | 872 | return SR_ERR_NA; |
a1c743fc BV |
873 | } |
874 | ||
875 | return SR_OK; | |
876 | } | |
877 | ||
36b1c8e6 HE |
878 | /* Software trigger to determine exact trigger position. */ |
879 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
880 | struct sigma_trigger *t) | |
881 | { | |
882 | int i; | |
883 | ||
884 | for (i = 0; i < 8; ++i) { | |
885 | if (i > 0) | |
886 | last_sample = samples[i-1]; | |
887 | ||
888 | /* Simple triggers. */ | |
889 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
890 | continue; | |
891 | ||
892 | /* Rising edge. */ | |
893 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
894 | t->risingmask) != t->risingmask) | |
895 | continue; | |
896 | ||
897 | /* Falling edge. */ | |
bdfc7a89 HE |
898 | if ((last_sample & t->fallingmask) != t->fallingmask || |
899 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
900 | continue; |
901 | ||
902 | break; | |
903 | } | |
904 | ||
905 | /* If we did not match, return original trigger pos. */ | |
906 | return i & 0x7; | |
907 | } | |
908 | ||
28a35d8a | 909 | /* |
fefa1800 UH |
910 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
911 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
912 | * |
913 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
914 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
915 | * For 50 MHz and below, events contain one sample for each channel, | |
916 | * spread 20 ns apart. | |
28a35d8a HE |
917 | */ |
918 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 919 | uint16_t *lastsample, int triggerpos, |
3cd3a20b | 920 | uint16_t limit_chunk, void *cb_data) |
28a35d8a | 921 | { |
3cd3a20b | 922 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 923 | struct dev_context *devc = sdi->priv; |
fefa1800 | 924 | uint16_t tsdiff, ts; |
0e1357e8 | 925 | uint16_t samples[65536 * devc->samples_per_event]; |
b9c735a2 | 926 | struct sr_datafeed_packet packet; |
9c939c51 | 927 | struct sr_datafeed_logic logic; |
f78898e9 | 928 | int i, j, k, l, numpad, tosend; |
fefa1800 | 929 | size_t n = 0, sent = 0; |
0e1357e8 | 930 | int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event; |
fefa1800 | 931 | uint16_t *event; |
f78898e9 | 932 | uint16_t cur_sample; |
57bbf56b | 933 | int triggerts = -1; |
ee492173 | 934 | |
4ae1f451 | 935 | /* Check if trigger is in this chunk. */ |
ee492173 | 936 | if (triggerpos != -1) { |
0e1357e8 | 937 | if (devc->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 938 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
939 | |
940 | if (triggerpos < 0) | |
941 | triggerpos = 0; | |
57bbf56b | 942 | |
ee492173 HE |
943 | /* Find in which cluster the trigger occured. */ |
944 | triggerts = triggerpos / 7; | |
945 | } | |
28a35d8a | 946 | |
eec5275e | 947 | /* For each ts. */ |
28a35d8a | 948 | for (i = 0; i < 64; ++i) { |
fefa1800 | 949 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
950 | tsdiff = ts - *lastts; |
951 | *lastts = ts; | |
952 | ||
88c51afe HE |
953 | /* Decode partial chunk. */ |
954 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 955 | return SR_OK; |
88c51afe | 956 | |
fefa1800 | 957 | /* Pad last sample up to current point. */ |
0e1357e8 | 958 | numpad = tsdiff * devc->samples_per_event - clustersize; |
28a35d8a | 959 | if (numpad > 0) { |
f78898e9 HE |
960 | for (j = 0; j < numpad; ++j) |
961 | samples[j] = *lastsample; | |
962 | ||
963 | n = numpad; | |
28a35d8a HE |
964 | } |
965 | ||
57bbf56b HE |
966 | /* Send samples between previous and this timestamp to sigrok. */ |
967 | sent = 0; | |
968 | while (sent < n) { | |
969 | tosend = MIN(2048, n - sent); | |
970 | ||
5a2326a7 | 971 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
972 | packet.payload = &logic; |
973 | logic.length = tosend * sizeof(uint16_t); | |
974 | logic.unitsize = 2; | |
975 | logic.data = samples + sent; | |
3e9b7f9c | 976 | sr_session_send(devc->cb_data, &packet); |
28a35d8a | 977 | |
57bbf56b HE |
978 | sent += tosend; |
979 | } | |
980 | n = 0; | |
981 | ||
982 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
983 | cur_sample = 0; |
984 | ||
985 | /* For each event in cluster. */ | |
28a35d8a | 986 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
987 | |
988 | /* For each sample in event. */ | |
0e1357e8 | 989 | for (k = 0; k < devc->samples_per_event; ++k) { |
f78898e9 HE |
990 | cur_sample = 0; |
991 | ||
ba7dd8bb UH |
992 | /* For each channel. */ |
993 | for (l = 0; l < devc->num_channels; ++l) | |
edca2c5c | 994 | cur_sample |= (!!(event[j] & (1 << (l * |
0e1357e8 | 995 | devc->samples_per_event + k)))) << l; |
f78898e9 HE |
996 | |
997 | samples[n++] = cur_sample; | |
28a35d8a HE |
998 | } |
999 | } | |
1000 | ||
eec5275e | 1001 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 1002 | sent = 0; |
57bbf56b HE |
1003 | if (i == triggerts) { |
1004 | /* | |
36b1c8e6 HE |
1005 | * Trigger is not always accurate to sample because of |
1006 | * pipeline delay. However, it always triggers before | |
1007 | * the actual event. We therefore look at the next | |
1008 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 1009 | */ |
bdfc7a89 | 1010 | tosend = get_trigger_offset(samples, *lastsample, |
0e1357e8 | 1011 | &devc->trigger); |
57bbf56b HE |
1012 | |
1013 | if (tosend > 0) { | |
5a2326a7 | 1014 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1015 | packet.payload = &logic; |
1016 | logic.length = tosend * sizeof(uint16_t); | |
1017 | logic.unitsize = 2; | |
1018 | logic.data = samples; | |
3e9b7f9c | 1019 | sr_session_send(devc->cb_data, &packet); |
57bbf56b HE |
1020 | |
1021 | sent += tosend; | |
1022 | } | |
28a35d8a | 1023 | |
5b5ea7c6 | 1024 | /* Only send trigger if explicitly enabled. */ |
0e1357e8 | 1025 | if (devc->use_triggers) { |
5a2326a7 | 1026 | packet.type = SR_DF_TRIGGER; |
3e9b7f9c | 1027 | sr_session_send(devc->cb_data, &packet); |
5b5ea7c6 | 1028 | } |
28a35d8a | 1029 | } |
57bbf56b | 1030 | |
eec5275e | 1031 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
1032 | tosend = n - sent; |
1033 | ||
abda62ce | 1034 | if (tosend > 0) { |
5a2326a7 | 1035 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1036 | packet.payload = &logic; |
1037 | logic.length = tosend * sizeof(uint16_t); | |
1038 | logic.unitsize = 2; | |
1039 | logic.data = samples + sent; | |
3e9b7f9c | 1040 | sr_session_send(devc->cb_data, &packet); |
abda62ce | 1041 | } |
ee492173 HE |
1042 | |
1043 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1044 | } |
1045 | ||
e46b8fb1 | 1046 | return SR_OK; |
28a35d8a HE |
1047 | } |
1048 | ||
6868626b | 1049 | static void download_capture(struct sr_dev_inst *sdi) |
28a35d8a | 1050 | { |
6868626b | 1051 | struct dev_context *devc; |
28a35d8a HE |
1052 | const int chunks_per_read = 32; |
1053 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6868626b BV |
1054 | int bufsz, i, numchunks, newchunks; |
1055 | ||
1056 | sr_info("Downloading sample data."); | |
1057 | ||
1058 | devc = sdi->priv; | |
1059 | devc->state.chunks_downloaded = 0; | |
1060 | numchunks = (devc->state.stoppos + 511) / 512; | |
1061 | newchunks = MIN(chunks_per_read, numchunks - devc->state.chunks_downloaded); | |
1062 | ||
1063 | bufsz = sigma_read_dram(devc->state.chunks_downloaded, newchunks, buf, devc); | |
1064 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ | |
1065 | (void)bufsz; | |
1066 | ||
1067 | /* Find first ts. */ | |
1068 | if (devc->state.chunks_downloaded == 0) { | |
1069 | devc->state.lastts = RL16(buf) - 1; | |
1070 | devc->state.lastsample = 0; | |
1071 | } | |
1072 | ||
1073 | /* Decode chunks and send them to sigrok. */ | |
1074 | for (i = 0; i < newchunks; ++i) { | |
1075 | int limit_chunk = 0; | |
1076 | ||
1077 | /* The last chunk may potentially be only in part. */ | |
1078 | if (devc->state.chunks_downloaded == numchunks - 1) { | |
1079 | /* Find the last valid timestamp */ | |
1080 | limit_chunk = devc->state.stoppos % 512 + devc->state.lastts; | |
1081 | } | |
1082 | ||
1083 | if (devc->state.chunks_downloaded + i == devc->state.triggerchunk) | |
1084 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1085 | &devc->state.lastts, | |
1086 | &devc->state.lastsample, | |
1087 | devc->state.triggerpos & 0x1ff, | |
1088 | limit_chunk, sdi); | |
1089 | else | |
1090 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1091 | &devc->state.lastts, | |
1092 | &devc->state.lastsample, | |
1093 | -1, limit_chunk, sdi); | |
1094 | ||
1095 | ++devc->state.chunks_downloaded; | |
1096 | } | |
1097 | ||
1098 | } | |
1099 | ||
1100 | static int receive_data(int fd, int revents, void *cb_data) | |
1101 | { | |
1102 | struct sr_dev_inst *sdi; | |
1103 | struct dev_context *devc; | |
1104 | struct sr_datafeed_packet packet; | |
94ba4bd6 | 1105 | uint64_t running_msec; |
28a35d8a | 1106 | struct timeval tv; |
6868626b BV |
1107 | int numchunks; |
1108 | uint8_t modestatus; | |
28a35d8a | 1109 | |
cb93f8a9 UH |
1110 | (void)fd; |
1111 | (void)revents; | |
28a35d8a | 1112 | |
6868626b BV |
1113 | sdi = cb_data; |
1114 | devc = sdi->priv; | |
1115 | ||
805919b0 | 1116 | /* Get the current position. */ |
0e1357e8 | 1117 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); |
805919b0 | 1118 | |
0e1357e8 | 1119 | if (devc->state.state == SIGMA_IDLE) |
805919b0 | 1120 | return TRUE; |
28a35d8a | 1121 | |
0e1357e8 | 1122 | if (devc->state.state == SIGMA_CAPTURE) { |
6868626b BV |
1123 | numchunks = (devc->state.stoppos + 511) / 512; |
1124 | ||
6aac7737 HE |
1125 | /* Check if the timer has expired, or memory is full. */ |
1126 | gettimeofday(&tv, 0); | |
0e1357e8 BV |
1127 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + |
1128 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
28a35d8a | 1129 | |
0e1357e8 | 1130 | if (running_msec < devc->limit_msec && numchunks < 32767) |
6868626b | 1131 | /* Still capturing. */ |
6aac7737 | 1132 | return TRUE; |
6aac7737 | 1133 | |
6868626b BV |
1134 | /* Stop acquisition. */ |
1135 | sigma_set_register(WRITE_MODE, 0x11, devc); | |
28a35d8a | 1136 | |
6868626b BV |
1137 | /* Set SDRAM Read Enable. */ |
1138 | sigma_set_register(WRITE_MODE, 0x02, devc); | |
28a35d8a | 1139 | |
6868626b BV |
1140 | /* Get the current position. */ |
1141 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); | |
28a35d8a | 1142 | |
6868626b BV |
1143 | /* Check if trigger has fired. */ |
1144 | modestatus = sigma_get_register(READ_MODE, devc); | |
1145 | if (modestatus & 0x20) | |
1146 | devc->state.triggerchunk = devc->state.triggerpos / 512; | |
1147 | else | |
1148 | devc->state.triggerchunk = -1; | |
28a35d8a | 1149 | |
6868626b BV |
1150 | /* Transfer captured data from device. */ |
1151 | download_capture(sdi); | |
88c51afe | 1152 | |
6868626b BV |
1153 | /* All done. */ |
1154 | packet.type = SR_DF_END; | |
1155 | sr_session_send(sdi, &packet); | |
88c51afe | 1156 | |
6868626b | 1157 | dev_acquisition_stop(sdi, sdi); |
28a35d8a HE |
1158 | } |
1159 | ||
28a35d8a HE |
1160 | return TRUE; |
1161 | } | |
1162 | ||
c53d793f HE |
1163 | /* Build a LUT entry used by the trigger functions. */ |
1164 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1165 | { |
1166 | int i, j, k, bit; | |
1167 | ||
ba7dd8bb | 1168 | /* For each quad channel. */ |
ee492173 | 1169 | for (i = 0; i < 4; ++i) { |
c53d793f | 1170 | entry[i] = 0xffff; |
ee492173 | 1171 | |
f758d074 | 1172 | /* For each bit in LUT. */ |
ee492173 HE |
1173 | for (j = 0; j < 16; ++j) |
1174 | ||
ba7dd8bb | 1175 | /* For each channel in quad. */ |
ee492173 HE |
1176 | for (k = 0; k < 4; ++k) { |
1177 | bit = 1 << (i * 4 + k); | |
1178 | ||
c53d793f HE |
1179 | /* Set bit in entry */ |
1180 | if ((mask & bit) && | |
1181 | ((!(value & bit)) != | |
4ae1f451 | 1182 | (!(j & (1 << k))))) |
c53d793f | 1183 | entry[i] &= ~(1 << j); |
ee492173 HE |
1184 | } |
1185 | } | |
c53d793f | 1186 | } |
ee492173 | 1187 | |
c53d793f HE |
1188 | /* Add a logical function to LUT mask. */ |
1189 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1190 | int index, int neg, uint16_t *mask) | |
1191 | { | |
1192 | int i, j; | |
1193 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1194 | ||
1195 | memset(x, 0, 4 * sizeof(int)); | |
1196 | ||
1197 | /* Trigger detect condition. */ | |
1198 | switch (oper) { | |
1199 | case OP_LEVEL: | |
1200 | x[0][1] = 1; | |
1201 | x[1][1] = 1; | |
1202 | break; | |
1203 | case OP_NOT: | |
1204 | x[0][0] = 1; | |
1205 | x[1][0] = 1; | |
1206 | break; | |
1207 | case OP_RISE: | |
1208 | x[0][1] = 1; | |
1209 | break; | |
1210 | case OP_FALL: | |
1211 | x[1][0] = 1; | |
1212 | break; | |
1213 | case OP_RISEFALL: | |
1214 | x[0][1] = 1; | |
1215 | x[1][0] = 1; | |
1216 | break; | |
1217 | case OP_NOTRISE: | |
1218 | x[1][1] = 1; | |
1219 | x[0][0] = 1; | |
1220 | x[1][0] = 1; | |
1221 | break; | |
1222 | case OP_NOTFALL: | |
1223 | x[1][1] = 1; | |
1224 | x[0][0] = 1; | |
1225 | x[0][1] = 1; | |
1226 | break; | |
1227 | case OP_NOTRISEFALL: | |
1228 | x[1][1] = 1; | |
1229 | x[0][0] = 1; | |
1230 | break; | |
1231 | } | |
1232 | ||
1233 | /* Transpose if neg is set. */ | |
1234 | if (neg) { | |
ea9cfed7 | 1235 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1236 | for (j = 0; j < 2; ++j) { |
1237 | tmp = x[i][j]; | |
1238 | x[i][j] = x[1-i][1-j]; | |
1239 | x[1-i][1-j] = tmp; | |
1240 | } | |
ea9cfed7 | 1241 | } |
c53d793f HE |
1242 | } |
1243 | ||
1244 | /* Update mask with function. */ | |
1245 | for (i = 0; i < 16; ++i) { | |
1246 | a = (i >> (2 * index + 0)) & 1; | |
1247 | b = (i >> (2 * index + 1)) & 1; | |
1248 | ||
1249 | aset = (*mask >> i) & 1; | |
1250 | bset = x[b][a]; | |
1251 | ||
1252 | if (func == FUNC_AND || func == FUNC_NAND) | |
1253 | rset = aset & bset; | |
1254 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1255 | rset = aset | bset; | |
1256 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1257 | rset = aset ^ bset; | |
1258 | ||
1259 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1260 | rset = !rset; | |
1261 | ||
1262 | *mask &= ~(1 << i); | |
1263 | ||
1264 | if (rset) | |
1265 | *mask |= 1 << i; | |
1266 | } | |
1267 | } | |
1268 | ||
1269 | /* | |
1270 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1271 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1272 | * set at any time, but a full mask and value can be set (0/1). | |
1273 | */ | |
0e1357e8 | 1274 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1275 | { |
1276 | int i,j; | |
4ae1f451 | 1277 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1278 | |
1279 | memset(lut, 0, sizeof(struct triggerlut)); | |
1280 | ||
1281 | /* Contant for simple triggers. */ | |
1282 | lut->m4 = 0xa000; | |
1283 | ||
1284 | /* Value/mask trigger support. */ | |
0e1357e8 | 1285 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1286 | lut->m2d); |
c53d793f HE |
1287 | |
1288 | /* Rise/fall trigger support. */ | |
1289 | for (i = 0, j = 0; i < 16; ++i) { | |
0e1357e8 BV |
1290 | if (devc->trigger.risingmask & (1 << i) || |
1291 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1292 | masks[j++] = 1 << i; |
1293 | } | |
1294 | ||
1295 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1296 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1297 | ||
1298 | /* Add glue logic */ | |
1299 | if (masks[0] || masks[1]) { | |
1300 | /* Transition trigger. */ | |
0e1357e8 | 1301 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1302 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1303 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1304 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1305 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1306 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1307 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1308 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1309 | } else { | |
1310 | /* Only value/mask trigger. */ | |
1311 | lut->m3 = 0xffff; | |
1312 | } | |
ee492173 | 1313 | |
c53d793f | 1314 | /* Triggertype: event. */ |
ee492173 HE |
1315 | lut->params.selres = 3; |
1316 | ||
e46b8fb1 | 1317 | return SR_OK; |
ee492173 HE |
1318 | } |
1319 | ||
6078d2c9 | 1320 | static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1321 | { |
0e1357e8 | 1322 | struct dev_context *devc; |
9ddb2a12 | 1323 | struct clockselect_50 clockselect; |
82957b65 | 1324 | int frac, triggerpin, ret; |
f4abaa9f | 1325 | uint8_t triggerselect = 0; |
57bbf56b | 1326 | struct triggerinout triggerinout_conf; |
ee492173 | 1327 | struct triggerlut lut; |
28a35d8a | 1328 | |
e73ffd42 BV |
1329 | if (sdi->status != SR_ST_ACTIVE) |
1330 | return SR_ERR_DEV_CLOSED; | |
1331 | ||
0e1357e8 | 1332 | devc = sdi->priv; |
28a35d8a | 1333 | |
ba7dd8bb UH |
1334 | if (configure_channels(sdi) != SR_OK) { |
1335 | sr_err("Failed to configure channels."); | |
014359e3 BV |
1336 | return SR_ERR; |
1337 | } | |
1338 | ||
ea9cfed7 | 1339 | /* If the samplerate has not been set, default to 200 kHz. */ |
0e1357e8 | 1340 | if (devc->cur_firmware == -1) { |
82957b65 UH |
1341 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1342 | return ret; | |
1343 | } | |
e8397563 | 1344 | |
eec5275e | 1345 | /* Enter trigger programming mode. */ |
0e1357e8 | 1346 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); |
28a35d8a | 1347 | |
eec5275e | 1348 | /* 100 and 200 MHz mode. */ |
0e1357e8 BV |
1349 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
1350 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
57bbf56b | 1351 | |
a42aec7f HE |
1352 | /* Find which pin to trigger on from mask. */ |
1353 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
0e1357e8 | 1354 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & |
a42aec7f HE |
1355 | (1 << triggerpin)) |
1356 | break; | |
1357 | ||
1358 | /* Set trigger pin and light LED on trigger. */ | |
1359 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1360 | ||
1361 | /* Default rising edge. */ | |
0e1357e8 | 1362 | if (devc->trigger.fallingmask) |
a42aec7f | 1363 | triggerselect |= 1 << 3; |
57bbf56b | 1364 | |
eec5275e | 1365 | /* All other modes. */ |
0e1357e8 BV |
1366 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { |
1367 | build_basic_trigger(&lut, devc); | |
ee492173 | 1368 | |
0e1357e8 | 1369 | sigma_write_trigger_lut(&lut, devc); |
57bbf56b HE |
1370 | |
1371 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1372 | } | |
1373 | ||
eec5275e | 1374 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1375 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1376 | triggerinout_conf.trgout_bytrigger = 1; | |
1377 | triggerinout_conf.trgout_enable = 1; | |
1378 | ||
28a35d8a | 1379 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1380 | (uint8_t *) &triggerinout_conf, |
0e1357e8 | 1381 | sizeof(struct triggerinout), devc); |
28a35d8a | 1382 | |
eec5275e | 1383 | /* Go back to normal mode. */ |
0e1357e8 | 1384 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); |
28a35d8a | 1385 | |
edca2c5c | 1386 | /* Set clock select register. */ |
0e1357e8 | 1387 | if (devc->cur_samplerate == SR_MHZ(200)) |
ba7dd8bb | 1388 | /* Enable 4 channels. */ |
0e1357e8 BV |
1389 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); |
1390 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
ba7dd8bb | 1391 | /* Enable 8 channels. */ |
0e1357e8 | 1392 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); |
edca2c5c HE |
1393 | else { |
1394 | /* | |
9ddb2a12 | 1395 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1396 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1397 | */ |
0e1357e8 | 1398 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; |
edca2c5c | 1399 | |
9ddb2a12 UH |
1400 | clockselect.async = 0; |
1401 | clockselect.fraction = frac; | |
ba7dd8bb | 1402 | clockselect.disabled_channels = 0; |
edca2c5c HE |
1403 | |
1404 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1405 | (uint8_t *) &clockselect, |
0e1357e8 | 1406 | sizeof(clockselect), devc); |
edca2c5c HE |
1407 | } |
1408 | ||
fefa1800 | 1409 | /* Setup maximum post trigger time. */ |
99965709 | 1410 | sigma_set_register(WRITE_POST_TRIGGER, |
0e1357e8 | 1411 | (devc->capture_ratio * 255) / 100, devc); |
28a35d8a | 1412 | |
eec5275e | 1413 | /* Start acqusition. */ |
0e1357e8 BV |
1414 | gettimeofday(&devc->start_tv, 0); |
1415 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
99965709 | 1416 | |
3e9b7f9c | 1417 | devc->cb_data = cb_data; |
28a35d8a | 1418 | |
3c36c403 | 1419 | /* Send header packet to the session bus. */ |
29a27196 | 1420 | std_session_send_df_header(cb_data, LOG_PREFIX); |
f366e86c | 1421 | |
f366e86c | 1422 | /* Add capture source. */ |
3ffb6964 | 1423 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); |
f366e86c | 1424 | |
0e1357e8 | 1425 | devc->state.state = SIGMA_CAPTURE; |
6aac7737 | 1426 | |
e46b8fb1 | 1427 | return SR_OK; |
28a35d8a HE |
1428 | } |
1429 | ||
6078d2c9 | 1430 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1431 | { |
0e1357e8 | 1432 | struct dev_context *devc; |
6aac7737 | 1433 | |
3cd3a20b | 1434 | (void)cb_data; |
28a35d8a | 1435 | |
6868626b BV |
1436 | devc = sdi->priv; |
1437 | devc->state.state = SIGMA_IDLE; | |
6aac7737 | 1438 | |
6868626b | 1439 | sr_source_remove(0); |
3010f21c UH |
1440 | |
1441 | return SR_OK; | |
28a35d8a HE |
1442 | } |
1443 | ||
c09f0b57 | 1444 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 | 1445 | .name = "asix-sigma", |
6352d030 | 1446 | .longname = "ASIX SIGMA/SIGMA2", |
e519ba86 | 1447 | .api_version = 1, |
6078d2c9 UH |
1448 | .init = init, |
1449 | .cleanup = cleanup, | |
1450 | .scan = scan, | |
1451 | .dev_list = dev_list, | |
3b412e3a | 1452 | .dev_clear = dev_clear, |
035a1078 BV |
1453 | .config_get = config_get, |
1454 | .config_set = config_set, | |
a1c743fc | 1455 | .config_list = config_list, |
6078d2c9 UH |
1456 | .dev_open = dev_open, |
1457 | .dev_close = dev_close, | |
1458 | .dev_acquisition_start = dev_acquisition_start, | |
1459 | .dev_acquisition_stop = dev_acquisition_stop, | |
0e1357e8 | 1460 | .priv = NULL, |
28a35d8a | 1461 | }; |