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Commit | Line | Data |
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28a35d8a | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
28a35d8a | 3 | * |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
45c59c8b BV |
30 | #include "libsigrok.h" |
31 | #include "libsigrok-internal.h" | |
28a35d8a HE |
32 | #include "asix-sigma.h" |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
c50277a6 | 39 | #define TRIGGER_TYPE "rf10" |
3f239f08 | 40 | #define NUM_CHANNELS 16 |
28a35d8a | 41 | |
ed300b9f | 42 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; |
a873c594 | 43 | static struct sr_dev_driver *di = &asix_sigma_driver_info; |
6078d2c9 | 44 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data); |
28a35d8a | 45 | |
b1648dea MV |
46 | /* |
47 | * The ASIX Sigma supports arbitrary integer frequency divider in | |
48 | * the 50MHz mode. The divider is in range 1...256 , allowing for | |
49 | * very precise sampling rate selection. This driver supports only | |
50 | * a subset of the sampling rates. | |
51 | */ | |
2c9c0df8 | 52 | static const uint64_t samplerates[] = { |
b1648dea MV |
53 | SR_KHZ(200), /* div=250 */ |
54 | SR_KHZ(250), /* div=200 */ | |
55 | SR_KHZ(500), /* div=100 */ | |
56 | SR_MHZ(1), /* div=50 */ | |
57 | SR_MHZ(5), /* div=10 */ | |
58 | SR_MHZ(10), /* div=5 */ | |
59 | SR_MHZ(25), /* div=2 */ | |
60 | SR_MHZ(50), /* div=1 */ | |
61 | SR_MHZ(100), /* Special FW needed */ | |
62 | SR_MHZ(200), /* Special FW needed */ | |
28a35d8a HE |
63 | }; |
64 | ||
d261dbbf | 65 | /* |
ba7dd8bb | 66 | * Channel numbers seem to go from 1-16, according to this image: |
d261dbbf UH |
67 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg |
68 | * (the cable has two additional GND pins, and a TI and TO pin) | |
69 | */ | |
3f239f08 | 70 | static const char *channel_names[NUM_CHANNELS + 1] = { |
78693401 UH |
71 | "1", "2", "3", "4", "5", "6", "7", "8", |
72 | "9", "10", "11", "12", "13", "14", "15", "16", | |
464d12c7 KS |
73 | NULL, |
74 | }; | |
75 | ||
2c9c0df8 | 76 | static const int32_t hwcaps[] = { |
1953564a BV |
77 | SR_CONF_LOGIC_ANALYZER, |
78 | SR_CONF_SAMPLERATE, | |
38d32464 | 79 | SR_CONF_TRIGGER_TYPE, |
1953564a | 80 | SR_CONF_CAPTURE_RATIO, |
1953564a | 81 | SR_CONF_LIMIT_MSEC, |
6868626b | 82 | SR_CONF_LIMIT_SAMPLES, |
28a35d8a HE |
83 | }; |
84 | ||
fefa1800 UH |
85 | /* Force the FPGA to reboot. */ |
86 | static uint8_t suicide[] = { | |
87 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
88 | }; | |
89 | ||
90 | /* Prepare to upload firmware (FPGA specific). */ | |
6078d2c9 | 91 | static uint8_t init_array[] = { |
fefa1800 UH |
92 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, |
93 | }; | |
94 | ||
95 | /* Initialize the logic analyzer mode. */ | |
96 | static uint8_t logic_mode_start[] = { | |
97 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
98 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
99 | }; | |
100 | ||
eec5275e | 101 | static const char *firmware_files[] = { |
a8116d76 HE |
102 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
103 | "asix-sigma-100.fw", /* 100 MHz */ | |
104 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 105 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 106 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
107 | }; |
108 | ||
0e1357e8 | 109 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
110 | { |
111 | int ret; | |
fefa1800 | 112 | |
0e1357e8 | 113 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 114 | if (ret < 0) { |
47f4f073 | 115 | sr_err("ftdi_read_data failed: %s", |
0e1357e8 | 116 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
117 | } |
118 | ||
119 | return ret; | |
120 | } | |
121 | ||
0e1357e8 | 122 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
123 | { |
124 | int ret; | |
fefa1800 | 125 | |
0e1357e8 | 126 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 127 | if (ret < 0) { |
47f4f073 | 128 | sr_err("ftdi_write_data failed: %s", |
0e1357e8 | 129 | ftdi_get_error_string(&devc->ftdic)); |
fefa1800 | 130 | } else if ((size_t) ret != size) { |
47f4f073 | 131 | sr_err("ftdi_write_data did not complete write."); |
28a35d8a HE |
132 | } |
133 | ||
134 | return ret; | |
135 | } | |
136 | ||
99965709 | 137 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 138 | struct dev_context *devc) |
28a35d8a HE |
139 | { |
140 | size_t i; | |
141 | uint8_t buf[len + 2]; | |
142 | int idx = 0; | |
143 | ||
144 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
145 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
146 | ||
fefa1800 | 147 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
148 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
149 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
150 | } | |
151 | ||
0e1357e8 | 152 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
153 | } |
154 | ||
0e1357e8 | 155 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 156 | { |
0e1357e8 | 157 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
158 | } |
159 | ||
99965709 | 160 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 161 | struct dev_context *devc) |
28a35d8a HE |
162 | { |
163 | uint8_t buf[3]; | |
fefa1800 | 164 | |
28a35d8a HE |
165 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
166 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
167 | buf[2] = REG_READ_ADDR; |
168 | ||
0e1357e8 | 169 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 170 | |
0e1357e8 | 171 | return sigma_read(data, len, devc); |
28a35d8a HE |
172 | } |
173 | ||
0e1357e8 | 174 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) |
28a35d8a HE |
175 | { |
176 | uint8_t value; | |
fefa1800 | 177 | |
0e1357e8 | 178 | if (1 != sigma_read_register(reg, &value, 1, devc)) { |
47f4f073 | 179 | sr_err("sigma_get_register: 1 byte expected"); |
28a35d8a HE |
180 | return 0; |
181 | } | |
182 | ||
183 | return value; | |
184 | } | |
185 | ||
99965709 | 186 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 187 | struct dev_context *devc) |
28a35d8a HE |
188 | { |
189 | uint8_t buf[] = { | |
190 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
191 | ||
192 | REG_READ_ADDR | NEXT_REG, | |
193 | REG_READ_ADDR | NEXT_REG, | |
194 | REG_READ_ADDR | NEXT_REG, | |
195 | REG_READ_ADDR | NEXT_REG, | |
196 | REG_READ_ADDR | NEXT_REG, | |
197 | REG_READ_ADDR | NEXT_REG, | |
198 | }; | |
28a35d8a HE |
199 | uint8_t result[6]; |
200 | ||
0e1357e8 | 201 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 202 | |
0e1357e8 | 203 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
204 | |
205 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
206 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
207 | ||
57bbf56b HE |
208 | /* Not really sure why this must be done, but according to spec. */ |
209 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
210 | stoppos -= 64; | |
211 | ||
212 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
213 | triggerpos -= 64; | |
214 | ||
28a35d8a HE |
215 | return 1; |
216 | } | |
217 | ||
99965709 | 218 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 219 | uint8_t *data, struct dev_context *devc) |
28a35d8a HE |
220 | { |
221 | size_t i; | |
222 | uint8_t buf[4096]; | |
223 | int idx = 0; | |
224 | ||
fefa1800 | 225 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
226 | buf[0] = startchunk >> 8; |
227 | buf[1] = startchunk & 0xff; | |
0e1357e8 | 228 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); |
28a35d8a | 229 | |
fefa1800 | 230 | /* Read the DRAM. */ |
28a35d8a HE |
231 | buf[idx++] = REG_DRAM_BLOCK; |
232 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
233 | ||
234 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
235 | /* Alternate bit to copy from DRAM to cache. */ |
236 | if (i != (numchunks - 1)) | |
237 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
238 | |
239 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
240 | ||
fefa1800 | 241 | if (i != (numchunks - 1)) |
28a35d8a HE |
242 | buf[idx++] = REG_DRAM_WAIT_ACK; |
243 | } | |
244 | ||
0e1357e8 | 245 | sigma_write(buf, idx, devc); |
28a35d8a | 246 | |
0e1357e8 | 247 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); |
28a35d8a HE |
248 | } |
249 | ||
4ae1f451 | 250 | /* Upload trigger look-up tables to Sigma. */ |
0e1357e8 | 251 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
252 | { |
253 | int i; | |
254 | uint8_t tmp[2]; | |
255 | uint16_t bit; | |
256 | ||
257 | /* Transpose the table and send to Sigma. */ | |
258 | for (i = 0; i < 16; ++i) { | |
259 | bit = 1 << i; | |
260 | ||
261 | tmp[0] = tmp[1] = 0; | |
262 | ||
263 | if (lut->m2d[0] & bit) | |
264 | tmp[0] |= 0x01; | |
265 | if (lut->m2d[1] & bit) | |
266 | tmp[0] |= 0x02; | |
267 | if (lut->m2d[2] & bit) | |
268 | tmp[0] |= 0x04; | |
269 | if (lut->m2d[3] & bit) | |
270 | tmp[0] |= 0x08; | |
271 | ||
272 | if (lut->m3 & bit) | |
273 | tmp[0] |= 0x10; | |
274 | if (lut->m3s & bit) | |
275 | tmp[0] |= 0x20; | |
276 | if (lut->m4 & bit) | |
277 | tmp[0] |= 0x40; | |
278 | ||
279 | if (lut->m0d[0] & bit) | |
280 | tmp[1] |= 0x01; | |
281 | if (lut->m0d[1] & bit) | |
282 | tmp[1] |= 0x02; | |
283 | if (lut->m0d[2] & bit) | |
284 | tmp[1] |= 0x04; | |
285 | if (lut->m0d[3] & bit) | |
286 | tmp[1] |= 0x08; | |
287 | ||
288 | if (lut->m1d[0] & bit) | |
289 | tmp[1] |= 0x10; | |
290 | if (lut->m1d[1] & bit) | |
291 | tmp[1] |= 0x20; | |
292 | if (lut->m1d[2] & bit) | |
293 | tmp[1] |= 0x40; | |
294 | if (lut->m1d[3] & bit) | |
295 | tmp[1] |= 0x80; | |
296 | ||
99965709 | 297 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
0e1357e8 BV |
298 | devc); |
299 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
ee492173 HE |
300 | } |
301 | ||
302 | /* Send the parameters */ | |
303 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
0e1357e8 | 304 | sizeof(lut->params), devc); |
ee492173 | 305 | |
e46b8fb1 | 306 | return SR_OK; |
ee492173 HE |
307 | } |
308 | ||
fefa1800 | 309 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 310 | static int bin2bitbang(const char *filename, |
fefa1800 | 311 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 312 | { |
fefa1800 | 313 | FILE *f; |
e3fff420 | 314 | unsigned long file_size; |
28a35d8a HE |
315 | unsigned long offset = 0; |
316 | unsigned char *p; | |
e3fff420 HE |
317 | uint8_t *firmware; |
318 | unsigned long fwsize = 0; | |
28a35d8a HE |
319 | const int buffer_size = 65536; |
320 | size_t i; | |
e3fff420 | 321 | int c, bit, v; |
fefa1800 | 322 | uint32_t imm = 0x3f6df2ab; |
28a35d8a | 323 | |
868d8cef | 324 | f = g_fopen(filename, "rb"); |
28a35d8a | 325 | if (!f) { |
47f4f073 | 326 | sr_err("g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 327 | return SR_ERR; |
28a35d8a HE |
328 | } |
329 | ||
330 | if (-1 == fseek(f, 0, SEEK_END)) { | |
47f4f073 | 331 | sr_err("fseek on %s failed", filename); |
28a35d8a | 332 | fclose(f); |
b53738ba | 333 | return SR_ERR; |
28a35d8a HE |
334 | } |
335 | ||
336 | file_size = ftell(f); | |
337 | ||
338 | fseek(f, 0, SEEK_SET); | |
339 | ||
b53738ba | 340 | if (!(firmware = g_try_malloc(buffer_size))) { |
47f4f073 | 341 | sr_err("%s: firmware malloc failed", __func__); |
12ad53f5 | 342 | fclose(f); |
b53738ba | 343 | return SR_ERR_MALLOC; |
28a35d8a HE |
344 | } |
345 | ||
28a35d8a HE |
346 | while ((c = getc(f)) != EOF) { |
347 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
e3fff420 | 348 | firmware[fwsize++] = c ^ imm; |
28a35d8a HE |
349 | } |
350 | fclose(f); | |
351 | ||
e3fff420 | 352 | if(fwsize != file_size) { |
47f4f073 | 353 | sr_err("%s: Error reading firmware", filename); |
e3fff420 HE |
354 | fclose(f); |
355 | g_free(firmware); | |
356 | return SR_ERR; | |
28a35d8a HE |
357 | } |
358 | ||
28a35d8a HE |
359 | *buf_size = fwsize * 2 * 8; |
360 | ||
b53738ba | 361 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 362 | if (!p) { |
47f4f073 | 363 | sr_err("%s: buf/p malloc failed", __func__); |
12ad53f5 | 364 | g_free(firmware); |
b53738ba | 365 | return SR_ERR_MALLOC; |
28a35d8a HE |
366 | } |
367 | ||
368 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 369 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 370 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
371 | p[offset++] = v | 0x01; |
372 | p[offset++] = v; | |
373 | } | |
374 | } | |
375 | ||
376 | g_free(firmware); | |
377 | ||
378 | if (offset != *buf_size) { | |
379 | g_free(*buf); | |
47f4f073 | 380 | sr_err("Error reading firmware %s " |
0aeb0ccd | 381 | "offset=%ld, file_size=%ld, buf_size=%zd.", |
133a37bf | 382 | filename, offset, file_size, *buf_size); |
28a35d8a | 383 | |
b53738ba | 384 | return SR_ERR; |
28a35d8a HE |
385 | } |
386 | ||
b53738ba | 387 | return SR_OK; |
28a35d8a HE |
388 | } |
389 | ||
3678cf73 | 390 | static void clear_helper(void *priv) |
0448d110 | 391 | { |
0e1357e8 | 392 | struct dev_context *devc; |
ce4d26dd | 393 | |
3678cf73 | 394 | devc = priv; |
0e1357e8 | 395 | |
3678cf73 UH |
396 | ftdi_deinit(&devc->ftdic); |
397 | } | |
0448d110 | 398 | |
3b412e3a | 399 | static int dev_clear(void) |
3678cf73 UH |
400 | { |
401 | return std_dev_clear(di, clear_helper); | |
0448d110 BV |
402 | } |
403 | ||
6078d2c9 | 404 | static int init(struct sr_context *sr_ctx) |
61136ea6 | 405 | { |
f6beaac5 | 406 | return std_init(sr_ctx, di, LOG_PREFIX); |
61136ea6 BV |
407 | } |
408 | ||
6078d2c9 | 409 | static GSList *scan(GSList *options) |
28a35d8a | 410 | { |
d68e2d1a | 411 | struct sr_dev_inst *sdi; |
ba7dd8bb | 412 | struct sr_channel *ch; |
0e1357e8 BV |
413 | struct drv_context *drvc; |
414 | struct dev_context *devc; | |
0448d110 | 415 | GSList *devices; |
e3fff420 HE |
416 | struct ftdi_device_list *devlist; |
417 | char serial_txt[10]; | |
418 | uint32_t serial; | |
87ca93c5 | 419 | int ret, i; |
28a35d8a | 420 | |
0448d110 | 421 | (void)options; |
64d33dc2 | 422 | |
a873c594 | 423 | drvc = di->priv; |
4b97c74e | 424 | |
0448d110 | 425 | devices = NULL; |
4b97c74e | 426 | |
0e1357e8 | 427 | if (!(devc = g_try_malloc(sizeof(struct dev_context)))) { |
47f4f073 | 428 | sr_err("%s: devc malloc failed", __func__); |
0448d110 | 429 | return NULL; |
b53738ba | 430 | } |
99965709 | 431 | |
0e1357e8 | 432 | ftdi_init(&devc->ftdic); |
28a35d8a | 433 | |
fefa1800 | 434 | /* Look for SIGMAs. */ |
e3fff420 | 435 | |
0e1357e8 | 436 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, |
eec944c5 BV |
437 | USB_VENDOR, USB_PRODUCT)) <= 0) { |
438 | if (ret < 0) | |
439 | sr_err("ftdi_usb_find_all(): %d", ret); | |
99965709 | 440 | goto free; |
eec944c5 | 441 | } |
99965709 | 442 | |
e3fff420 | 443 | /* Make sure it's a version 1 or 2 SIGMA. */ |
0e1357e8 | 444 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, |
6352d030 | 445 | serial_txt, sizeof(serial_txt)); |
e3fff420 HE |
446 | sscanf(serial_txt, "%x", &serial); |
447 | ||
6352d030 | 448 | if (serial < 0xa6010000 || serial > 0xa602ffff) { |
47f4f073 UH |
449 | sr_err("Only SIGMA and SIGMA2 are supported " |
450 | "in this version of libsigrok."); | |
e3fff420 HE |
451 | goto free; |
452 | } | |
453 | ||
454 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
455 | ||
0e1357e8 BV |
456 | devc->cur_samplerate = 0; |
457 | devc->period_ps = 0; | |
458 | devc->limit_msec = 0; | |
459 | devc->cur_firmware = -1; | |
ba7dd8bb | 460 | devc->num_channels = 0; |
0e1357e8 BV |
461 | devc->samples_per_event = 0; |
462 | devc->capture_ratio = 50; | |
463 | devc->use_triggers = 0; | |
28a35d8a | 464 | |
fefa1800 | 465 | /* Register SIGMA device. */ |
d68e2d1a | 466 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
55f98c65 | 467 | USB_MODEL_NAME, NULL))) { |
47f4f073 | 468 | sr_err("%s: sdi was NULL", __func__); |
99965709 | 469 | goto free; |
d68e2d1a | 470 | } |
a873c594 | 471 | sdi->driver = di; |
87ca93c5 | 472 | |
ba7dd8bb | 473 | for (i = 0; channel_names[i]; i++) { |
3f239f08 | 474 | if (!(ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE, |
ba7dd8bb | 475 | channel_names[i]))) |
87ca93c5 | 476 | return NULL; |
ba7dd8bb | 477 | sdi->channels = g_slist_append(sdi->channels, ch); |
87ca93c5 BV |
478 | } |
479 | ||
0448d110 | 480 | devices = g_slist_append(devices, sdi); |
0e1357e8 BV |
481 | drvc->instances = g_slist_append(drvc->instances, sdi); |
482 | sdi->priv = devc; | |
28a35d8a | 483 | |
fefa1800 | 484 | /* We will open the device again when we need it. */ |
e3fff420 | 485 | ftdi_list_free(&devlist); |
28a35d8a | 486 | |
0448d110 | 487 | return devices; |
ea9cfed7 | 488 | |
99965709 | 489 | free: |
0e1357e8 BV |
490 | ftdi_deinit(&devc->ftdic); |
491 | g_free(devc); | |
0448d110 | 492 | return NULL; |
28a35d8a HE |
493 | } |
494 | ||
6078d2c9 | 495 | static GSList *dev_list(void) |
811deee4 | 496 | { |
0e94d524 | 497 | return ((struct drv_context *)(di->priv))->instances; |
811deee4 BV |
498 | } |
499 | ||
0e1357e8 | 500 | static int upload_firmware(int firmware_idx, struct dev_context *devc) |
28a35d8a HE |
501 | { |
502 | int ret; | |
503 | unsigned char *buf; | |
504 | unsigned char pins; | |
505 | size_t buf_size; | |
28a35d8a | 506 | unsigned char result[32]; |
e8397563 | 507 | char firmware_path[128]; |
28a35d8a | 508 | |
fefa1800 | 509 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 510 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
28a35d8a | 511 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
47f4f073 | 512 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 513 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
514 | return 0; |
515 | } | |
516 | ||
0e1357e8 | 517 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
47f4f073 | 518 | sr_err("ftdi_set_bitmode failed: %s", |
0e1357e8 | 519 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
520 | return 0; |
521 | } | |
522 | ||
fefa1800 | 523 | /* Four times the speed of sigmalogan - Works well. */ |
0e1357e8 | 524 | if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) { |
47f4f073 | 525 | sr_err("ftdi_set_baudrate failed: %s", |
0e1357e8 | 526 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
527 | return 0; |
528 | } | |
529 | ||
fefa1800 | 530 | /* Force the FPGA to reboot. */ |
0e1357e8 BV |
531 | sigma_write(suicide, sizeof(suicide), devc); |
532 | sigma_write(suicide, sizeof(suicide), devc); | |
533 | sigma_write(suicide, sizeof(suicide), devc); | |
534 | sigma_write(suicide, sizeof(suicide), devc); | |
28a35d8a | 535 | |
fefa1800 | 536 | /* Prepare to upload firmware (FPGA specific). */ |
6078d2c9 | 537 | sigma_write(init_array, sizeof(init_array), devc); |
28a35d8a | 538 | |
0e1357e8 | 539 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 540 | |
fefa1800 | 541 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 542 | while (1) { |
0e1357e8 | 543 | ret = sigma_read(result, 1, devc); |
28a35d8a HE |
544 | if (result[0] & 0x20) |
545 | break; | |
546 | } | |
547 | ||
9ddb2a12 | 548 | /* Prepare firmware. */ |
e8397563 | 549 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
550 | firmware_files[firmware_idx]); |
551 | ||
b53738ba | 552 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { |
47f4f073 | 553 | sr_err("An error occured while reading the firmware: %s", |
133a37bf | 554 | firmware_path); |
b53738ba | 555 | return ret; |
28a35d8a HE |
556 | } |
557 | ||
fefa1800 | 558 | /* Upload firmare. */ |
47f4f073 | 559 | sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]); |
0e1357e8 | 560 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
561 | |
562 | g_free(buf); | |
563 | ||
0e1357e8 | 564 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) { |
47f4f073 | 565 | sr_err("ftdi_set_bitmode failed: %s", |
0e1357e8 | 566 | ftdi_get_error_string(&devc->ftdic)); |
e46b8fb1 | 567 | return SR_ERR; |
28a35d8a HE |
568 | } |
569 | ||
0e1357e8 | 570 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 571 | |
fefa1800 | 572 | /* Discard garbage. */ |
0e1357e8 | 573 | while (1 == sigma_read(&pins, 1, devc)) |
28a35d8a HE |
574 | ; |
575 | ||
fefa1800 | 576 | /* Initialize the logic analyzer mode. */ |
0e1357e8 | 577 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); |
28a35d8a | 578 | |
fefa1800 | 579 | /* Expect a 3 byte reply. */ |
0e1357e8 | 580 | ret = sigma_read(result, 3, devc); |
28a35d8a HE |
581 | if (ret != 3 || |
582 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
47f4f073 | 583 | sr_err("Configuration failed. Invalid reply received."); |
e46b8fb1 | 584 | return SR_ERR; |
28a35d8a HE |
585 | } |
586 | ||
0e1357e8 | 587 | devc->cur_firmware = firmware_idx; |
f6564c8d | 588 | |
47f4f073 | 589 | sr_info("Firmware uploaded."); |
e3fff420 | 590 | |
e46b8fb1 | 591 | return SR_OK; |
f6564c8d HE |
592 | } |
593 | ||
6078d2c9 | 594 | static int dev_open(struct sr_dev_inst *sdi) |
f6564c8d | 595 | { |
0e1357e8 | 596 | struct dev_context *devc; |
f6564c8d HE |
597 | int ret; |
598 | ||
0e1357e8 | 599 | devc = sdi->priv; |
99965709 | 600 | |
9ddb2a12 | 601 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 602 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
f6564c8d HE |
603 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
604 | ||
47f4f073 | 605 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 606 | ftdi_get_error_string(&devc->ftdic)); |
f6564c8d HE |
607 | |
608 | return 0; | |
609 | } | |
28a35d8a | 610 | |
5a2326a7 | 611 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 612 | |
e46b8fb1 | 613 | return SR_OK; |
f6564c8d HE |
614 | } |
615 | ||
6f4b1868 | 616 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 617 | { |
2c9c0df8 BV |
618 | struct dev_context *devc; |
619 | unsigned int i; | |
620 | int ret; | |
f6564c8d | 621 | |
2c9c0df8 | 622 | devc = sdi->priv; |
f4abaa9f UH |
623 | ret = SR_OK; |
624 | ||
2c9c0df8 BV |
625 | for (i = 0; i < ARRAY_SIZE(samplerates); i++) { |
626 | if (samplerates[i] == samplerate) | |
f6564c8d HE |
627 | break; |
628 | } | |
2c9c0df8 | 629 | if (samplerates[i] == 0) |
e46b8fb1 | 630 | return SR_ERR_SAMPLERATE; |
f6564c8d | 631 | |
59df0c77 | 632 | if (samplerate <= SR_MHZ(50)) { |
0e1357e8 | 633 | ret = upload_firmware(0, devc); |
ba7dd8bb | 634 | devc->num_channels = 16; |
e8397563 | 635 | } |
59df0c77 | 636 | if (samplerate == SR_MHZ(100)) { |
0e1357e8 | 637 | ret = upload_firmware(1, devc); |
ba7dd8bb | 638 | devc->num_channels = 8; |
f78898e9 | 639 | } |
59df0c77 | 640 | else if (samplerate == SR_MHZ(200)) { |
0e1357e8 | 641 | ret = upload_firmware(2, devc); |
ba7dd8bb | 642 | devc->num_channels = 4; |
f78898e9 | 643 | } |
f6564c8d | 644 | |
0e1357e8 | 645 | devc->cur_samplerate = samplerate; |
5edc02c7 | 646 | devc->period_ps = 1000000000000ULL / samplerate; |
ba7dd8bb | 647 | devc->samples_per_event = 16 / devc->num_channels; |
0e1357e8 | 648 | devc->state.state = SIGMA_IDLE; |
f6564c8d | 649 | |
e8397563 | 650 | return ret; |
28a35d8a HE |
651 | } |
652 | ||
c53d793f HE |
653 | /* |
654 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
655 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
ba7dd8bb | 656 | * in addition to value/mask trigger for any number of channels. |
c53d793f HE |
657 | * |
658 | * The Sigma supports complex triggers using boolean expressions, but this | |
659 | * has not been implemented yet. | |
660 | */ | |
ba7dd8bb | 661 | static int configure_channels(const struct sr_dev_inst *sdi) |
57bbf56b | 662 | { |
0e1357e8 | 663 | struct dev_context *devc = sdi->priv; |
ba7dd8bb | 664 | const struct sr_channel *ch; |
1b79df2f | 665 | const GSList *l; |
57bbf56b | 666 | int trigger_set = 0; |
ba7dd8bb | 667 | int channelbit; |
57bbf56b | 668 | |
0e1357e8 | 669 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 670 | |
ba7dd8bb UH |
671 | for (l = sdi->channels; l; l = l->next) { |
672 | ch = (struct sr_channel *)l->data; | |
673 | channelbit = 1 << (ch->index); | |
57bbf56b | 674 | |
ba7dd8bb | 675 | if (!ch->enabled || !ch->trigger) |
57bbf56b HE |
676 | continue; |
677 | ||
0e1357e8 | 678 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 679 | /* Fast trigger support. */ |
ee492173 | 680 | if (trigger_set) { |
47f4f073 UH |
681 | sr_err("Only a single pin trigger in 100 and " |
682 | "200MHz mode is supported."); | |
e46b8fb1 | 683 | return SR_ERR; |
ee492173 | 684 | } |
ba7dd8bb UH |
685 | if (ch->trigger[0] == 'f') |
686 | devc->trigger.fallingmask |= channelbit; | |
687 | else if (ch->trigger[0] == 'r') | |
688 | devc->trigger.risingmask |= channelbit; | |
ee492173 | 689 | else { |
47f4f073 UH |
690 | sr_err("Only rising/falling trigger in 100 " |
691 | "and 200MHz mode is supported."); | |
e46b8fb1 | 692 | return SR_ERR; |
ee492173 | 693 | } |
57bbf56b | 694 | |
c53d793f | 695 | ++trigger_set; |
ee492173 | 696 | } else { |
c53d793f | 697 | /* Simple trigger support (event). */ |
ba7dd8bb UH |
698 | if (ch->trigger[0] == '1') { |
699 | devc->trigger.simplevalue |= channelbit; | |
700 | devc->trigger.simplemask |= channelbit; | |
c53d793f | 701 | } |
ba7dd8bb UH |
702 | else if (ch->trigger[0] == '0') { |
703 | devc->trigger.simplevalue &= ~channelbit; | |
704 | devc->trigger.simplemask |= channelbit; | |
c53d793f | 705 | } |
ba7dd8bb UH |
706 | else if (ch->trigger[0] == 'f') { |
707 | devc->trigger.fallingmask |= channelbit; | |
c53d793f HE |
708 | ++trigger_set; |
709 | } | |
ba7dd8bb UH |
710 | else if (ch->trigger[0] == 'r') { |
711 | devc->trigger.risingmask |= channelbit; | |
c53d793f HE |
712 | ++trigger_set; |
713 | } | |
ee492173 | 714 | |
ea9cfed7 UH |
715 | /* |
716 | * Actually, Sigma supports 2 rising/falling triggers, | |
717 | * but they are ORed and the current trigger syntax | |
718 | * does not permit ORed triggers. | |
719 | */ | |
98b8cbc1 | 720 | if (trigger_set > 1) { |
47f4f073 UH |
721 | sr_err("Only 1 rising/falling trigger " |
722 | "is supported."); | |
e46b8fb1 | 723 | return SR_ERR; |
ee492173 | 724 | } |
ee492173 | 725 | } |
5b5ea7c6 HE |
726 | |
727 | if (trigger_set) | |
0e1357e8 | 728 | devc->use_triggers = 1; |
57bbf56b HE |
729 | } |
730 | ||
e46b8fb1 | 731 | return SR_OK; |
57bbf56b HE |
732 | } |
733 | ||
6078d2c9 | 734 | static int dev_close(struct sr_dev_inst *sdi) |
28a35d8a | 735 | { |
0e1357e8 | 736 | struct dev_context *devc; |
28a35d8a | 737 | |
961009b0 | 738 | devc = sdi->priv; |
697785d1 UH |
739 | |
740 | /* TODO */ | |
741 | if (sdi->status == SR_ST_ACTIVE) | |
0e1357e8 | 742 | ftdi_usb_close(&devc->ftdic); |
697785d1 UH |
743 | |
744 | sdi->status = SR_ST_INACTIVE; | |
745 | ||
746 | return SR_OK; | |
28a35d8a HE |
747 | } |
748 | ||
6078d2c9 | 749 | static int cleanup(void) |
28a35d8a | 750 | { |
3b412e3a | 751 | return dev_clear(); |
28a35d8a HE |
752 | } |
753 | ||
8f996b89 | 754 | static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi, |
53b4680f | 755 | const struct sr_channel_group *cg) |
28a35d8a | 756 | { |
0e1357e8 | 757 | struct dev_context *devc; |
99965709 | 758 | |
53b4680f | 759 | (void)cg; |
8f996b89 | 760 | |
035a1078 | 761 | switch (id) { |
123e1313 | 762 | case SR_CONF_SAMPLERATE: |
41479605 | 763 | if (sdi) { |
0e1357e8 | 764 | devc = sdi->priv; |
2c9c0df8 | 765 | *data = g_variant_new_uint64(devc->cur_samplerate); |
41479605 BV |
766 | } else |
767 | return SR_ERR; | |
28a35d8a | 768 | break; |
d7bbecfd | 769 | default: |
bd6fbf62 | 770 | return SR_ERR_NA; |
28a35d8a HE |
771 | } |
772 | ||
41479605 | 773 | return SR_OK; |
28a35d8a HE |
774 | } |
775 | ||
8f996b89 | 776 | static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi, |
53b4680f | 777 | const struct sr_channel_group *cg) |
28a35d8a | 778 | { |
0e1357e8 | 779 | struct dev_context *devc; |
6868626b | 780 | uint64_t num_samples; |
28a35d8a | 781 | int ret; |
f6564c8d | 782 | |
53b4680f | 783 | (void)cg; |
8f996b89 | 784 | |
e73ffd42 BV |
785 | if (sdi->status != SR_ST_ACTIVE) |
786 | return SR_ERR_DEV_CLOSED; | |
787 | ||
0e1357e8 | 788 | devc = sdi->priv; |
99965709 | 789 | |
6868626b BV |
790 | switch (id) { |
791 | case SR_CONF_SAMPLERATE: | |
2c9c0df8 | 792 | ret = set_samplerate(sdi, g_variant_get_uint64(data)); |
6868626b BV |
793 | break; |
794 | case SR_CONF_LIMIT_MSEC: | |
2c9c0df8 | 795 | devc->limit_msec = g_variant_get_uint64(data); |
0e1357e8 | 796 | if (devc->limit_msec > 0) |
e46b8fb1 | 797 | ret = SR_OK; |
94ba4bd6 | 798 | else |
e46b8fb1 | 799 | ret = SR_ERR; |
6868626b BV |
800 | break; |
801 | case SR_CONF_LIMIT_SAMPLES: | |
802 | num_samples = g_variant_get_uint64(data); | |
803 | devc->limit_msec = num_samples * 1000 / devc->cur_samplerate; | |
804 | break; | |
805 | case SR_CONF_CAPTURE_RATIO: | |
2c9c0df8 | 806 | devc->capture_ratio = g_variant_get_uint64(data); |
0e1357e8 | 807 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) |
e46b8fb1 | 808 | ret = SR_ERR; |
94ba4bd6 | 809 | else |
e46b8fb1 | 810 | ret = SR_OK; |
6868626b BV |
811 | break; |
812 | default: | |
bd6fbf62 | 813 | ret = SR_ERR_NA; |
28a35d8a HE |
814 | } |
815 | ||
816 | return ret; | |
817 | } | |
818 | ||
8f996b89 | 819 | static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi, |
53b4680f | 820 | const struct sr_channel_group *cg) |
a1c743fc | 821 | { |
2c9c0df8 BV |
822 | GVariant *gvar; |
823 | GVariantBuilder gvb; | |
a1c743fc BV |
824 | |
825 | (void)sdi; | |
53b4680f | 826 | (void)cg; |
a1c743fc BV |
827 | |
828 | switch (key) { | |
9a6517d1 | 829 | case SR_CONF_DEVICE_OPTIONS: |
2c9c0df8 BV |
830 | *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32, |
831 | hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t)); | |
9a6517d1 | 832 | break; |
a1c743fc | 833 | case SR_CONF_SAMPLERATE: |
2c9c0df8 BV |
834 | g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}")); |
835 | gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates, | |
836 | ARRAY_SIZE(samplerates), sizeof(uint64_t)); | |
837 | g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar); | |
838 | *data = g_variant_builder_end(&gvb); | |
a1c743fc | 839 | break; |
c50277a6 | 840 | case SR_CONF_TRIGGER_TYPE: |
2c9c0df8 | 841 | *data = g_variant_new_string(TRIGGER_TYPE); |
c50277a6 | 842 | break; |
a1c743fc | 843 | default: |
bd6fbf62 | 844 | return SR_ERR_NA; |
a1c743fc BV |
845 | } |
846 | ||
847 | return SR_OK; | |
848 | } | |
849 | ||
36b1c8e6 HE |
850 | /* Software trigger to determine exact trigger position. */ |
851 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
852 | struct sigma_trigger *t) | |
853 | { | |
854 | int i; | |
855 | ||
856 | for (i = 0; i < 8; ++i) { | |
857 | if (i > 0) | |
858 | last_sample = samples[i-1]; | |
859 | ||
860 | /* Simple triggers. */ | |
861 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
862 | continue; | |
863 | ||
864 | /* Rising edge. */ | |
865 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
866 | t->risingmask) != t->risingmask) | |
867 | continue; | |
868 | ||
869 | /* Falling edge. */ | |
bdfc7a89 HE |
870 | if ((last_sample & t->fallingmask) != t->fallingmask || |
871 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
872 | continue; |
873 | ||
874 | break; | |
875 | } | |
876 | ||
877 | /* If we did not match, return original trigger pos. */ | |
878 | return i & 0x7; | |
879 | } | |
880 | ||
28a35d8a | 881 | /* |
fefa1800 UH |
882 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
883 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
884 | * |
885 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
886 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
887 | * For 50 MHz and below, events contain one sample for each channel, | |
888 | * spread 20 ns apart. | |
28a35d8a HE |
889 | */ |
890 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 891 | uint16_t *lastsample, int triggerpos, |
3cd3a20b | 892 | uint16_t limit_chunk, void *cb_data) |
28a35d8a | 893 | { |
3cd3a20b | 894 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 895 | struct dev_context *devc = sdi->priv; |
fefa1800 | 896 | uint16_t tsdiff, ts; |
0e1357e8 | 897 | uint16_t samples[65536 * devc->samples_per_event]; |
b9c735a2 | 898 | struct sr_datafeed_packet packet; |
9c939c51 | 899 | struct sr_datafeed_logic logic; |
f78898e9 | 900 | int i, j, k, l, numpad, tosend; |
fefa1800 | 901 | size_t n = 0, sent = 0; |
0e1357e8 | 902 | int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event; |
fefa1800 | 903 | uint16_t *event; |
f78898e9 | 904 | uint16_t cur_sample; |
57bbf56b | 905 | int triggerts = -1; |
ee492173 | 906 | |
4ae1f451 | 907 | /* Check if trigger is in this chunk. */ |
ee492173 | 908 | if (triggerpos != -1) { |
0e1357e8 | 909 | if (devc->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 910 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
911 | |
912 | if (triggerpos < 0) | |
913 | triggerpos = 0; | |
57bbf56b | 914 | |
ee492173 HE |
915 | /* Find in which cluster the trigger occured. */ |
916 | triggerts = triggerpos / 7; | |
917 | } | |
28a35d8a | 918 | |
eec5275e | 919 | /* For each ts. */ |
28a35d8a | 920 | for (i = 0; i < 64; ++i) { |
fefa1800 | 921 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
922 | tsdiff = ts - *lastts; |
923 | *lastts = ts; | |
924 | ||
88c51afe HE |
925 | /* Decode partial chunk. */ |
926 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 927 | return SR_OK; |
88c51afe | 928 | |
fefa1800 | 929 | /* Pad last sample up to current point. */ |
0e1357e8 | 930 | numpad = tsdiff * devc->samples_per_event - clustersize; |
28a35d8a | 931 | if (numpad > 0) { |
f78898e9 HE |
932 | for (j = 0; j < numpad; ++j) |
933 | samples[j] = *lastsample; | |
934 | ||
935 | n = numpad; | |
28a35d8a HE |
936 | } |
937 | ||
57bbf56b HE |
938 | /* Send samples between previous and this timestamp to sigrok. */ |
939 | sent = 0; | |
940 | while (sent < n) { | |
941 | tosend = MIN(2048, n - sent); | |
942 | ||
5a2326a7 | 943 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
944 | packet.payload = &logic; |
945 | logic.length = tosend * sizeof(uint16_t); | |
946 | logic.unitsize = 2; | |
947 | logic.data = samples + sent; | |
3e9b7f9c | 948 | sr_session_send(devc->cb_data, &packet); |
28a35d8a | 949 | |
57bbf56b HE |
950 | sent += tosend; |
951 | } | |
952 | n = 0; | |
953 | ||
954 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
955 | cur_sample = 0; |
956 | ||
957 | /* For each event in cluster. */ | |
28a35d8a | 958 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
959 | |
960 | /* For each sample in event. */ | |
0e1357e8 | 961 | for (k = 0; k < devc->samples_per_event; ++k) { |
f78898e9 HE |
962 | cur_sample = 0; |
963 | ||
ba7dd8bb UH |
964 | /* For each channel. */ |
965 | for (l = 0; l < devc->num_channels; ++l) | |
edca2c5c | 966 | cur_sample |= (!!(event[j] & (1 << (l * |
0e1357e8 | 967 | devc->samples_per_event + k)))) << l; |
f78898e9 HE |
968 | |
969 | samples[n++] = cur_sample; | |
28a35d8a HE |
970 | } |
971 | } | |
972 | ||
eec5275e | 973 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 974 | sent = 0; |
57bbf56b HE |
975 | if (i == triggerts) { |
976 | /* | |
36b1c8e6 HE |
977 | * Trigger is not always accurate to sample because of |
978 | * pipeline delay. However, it always triggers before | |
979 | * the actual event. We therefore look at the next | |
980 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 981 | */ |
bdfc7a89 | 982 | tosend = get_trigger_offset(samples, *lastsample, |
0e1357e8 | 983 | &devc->trigger); |
57bbf56b HE |
984 | |
985 | if (tosend > 0) { | |
5a2326a7 | 986 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
987 | packet.payload = &logic; |
988 | logic.length = tosend * sizeof(uint16_t); | |
989 | logic.unitsize = 2; | |
990 | logic.data = samples; | |
3e9b7f9c | 991 | sr_session_send(devc->cb_data, &packet); |
57bbf56b HE |
992 | |
993 | sent += tosend; | |
994 | } | |
28a35d8a | 995 | |
5b5ea7c6 | 996 | /* Only send trigger if explicitly enabled. */ |
0e1357e8 | 997 | if (devc->use_triggers) { |
5a2326a7 | 998 | packet.type = SR_DF_TRIGGER; |
3e9b7f9c | 999 | sr_session_send(devc->cb_data, &packet); |
5b5ea7c6 | 1000 | } |
28a35d8a | 1001 | } |
57bbf56b | 1002 | |
eec5275e | 1003 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
1004 | tosend = n - sent; |
1005 | ||
abda62ce | 1006 | if (tosend > 0) { |
5a2326a7 | 1007 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1008 | packet.payload = &logic; |
1009 | logic.length = tosend * sizeof(uint16_t); | |
1010 | logic.unitsize = 2; | |
1011 | logic.data = samples + sent; | |
3e9b7f9c | 1012 | sr_session_send(devc->cb_data, &packet); |
abda62ce | 1013 | } |
ee492173 HE |
1014 | |
1015 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1016 | } |
1017 | ||
e46b8fb1 | 1018 | return SR_OK; |
28a35d8a HE |
1019 | } |
1020 | ||
6868626b | 1021 | static void download_capture(struct sr_dev_inst *sdi) |
28a35d8a | 1022 | { |
6868626b | 1023 | struct dev_context *devc; |
28a35d8a HE |
1024 | const int chunks_per_read = 32; |
1025 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6868626b BV |
1026 | int bufsz, i, numchunks, newchunks; |
1027 | ||
1028 | sr_info("Downloading sample data."); | |
1029 | ||
1030 | devc = sdi->priv; | |
1031 | devc->state.chunks_downloaded = 0; | |
1032 | numchunks = (devc->state.stoppos + 511) / 512; | |
1033 | newchunks = MIN(chunks_per_read, numchunks - devc->state.chunks_downloaded); | |
1034 | ||
1035 | bufsz = sigma_read_dram(devc->state.chunks_downloaded, newchunks, buf, devc); | |
1036 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ | |
1037 | (void)bufsz; | |
1038 | ||
1039 | /* Find first ts. */ | |
1040 | if (devc->state.chunks_downloaded == 0) { | |
1041 | devc->state.lastts = RL16(buf) - 1; | |
1042 | devc->state.lastsample = 0; | |
1043 | } | |
1044 | ||
1045 | /* Decode chunks and send them to sigrok. */ | |
1046 | for (i = 0; i < newchunks; ++i) { | |
1047 | int limit_chunk = 0; | |
1048 | ||
1049 | /* The last chunk may potentially be only in part. */ | |
1050 | if (devc->state.chunks_downloaded == numchunks - 1) { | |
1051 | /* Find the last valid timestamp */ | |
1052 | limit_chunk = devc->state.stoppos % 512 + devc->state.lastts; | |
1053 | } | |
1054 | ||
1055 | if (devc->state.chunks_downloaded + i == devc->state.triggerchunk) | |
1056 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1057 | &devc->state.lastts, | |
1058 | &devc->state.lastsample, | |
1059 | devc->state.triggerpos & 0x1ff, | |
1060 | limit_chunk, sdi); | |
1061 | else | |
1062 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1063 | &devc->state.lastts, | |
1064 | &devc->state.lastsample, | |
1065 | -1, limit_chunk, sdi); | |
1066 | ||
1067 | ++devc->state.chunks_downloaded; | |
1068 | } | |
1069 | ||
1070 | } | |
1071 | ||
1072 | static int receive_data(int fd, int revents, void *cb_data) | |
1073 | { | |
1074 | struct sr_dev_inst *sdi; | |
1075 | struct dev_context *devc; | |
1076 | struct sr_datafeed_packet packet; | |
94ba4bd6 | 1077 | uint64_t running_msec; |
28a35d8a | 1078 | struct timeval tv; |
6868626b BV |
1079 | int numchunks; |
1080 | uint8_t modestatus; | |
28a35d8a | 1081 | |
cb93f8a9 UH |
1082 | (void)fd; |
1083 | (void)revents; | |
28a35d8a | 1084 | |
6868626b BV |
1085 | sdi = cb_data; |
1086 | devc = sdi->priv; | |
1087 | ||
805919b0 | 1088 | /* Get the current position. */ |
0e1357e8 | 1089 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); |
805919b0 | 1090 | |
0e1357e8 | 1091 | if (devc->state.state == SIGMA_IDLE) |
805919b0 | 1092 | return TRUE; |
28a35d8a | 1093 | |
0e1357e8 | 1094 | if (devc->state.state == SIGMA_CAPTURE) { |
6868626b BV |
1095 | numchunks = (devc->state.stoppos + 511) / 512; |
1096 | ||
6aac7737 HE |
1097 | /* Check if the timer has expired, or memory is full. */ |
1098 | gettimeofday(&tv, 0); | |
0e1357e8 BV |
1099 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + |
1100 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
28a35d8a | 1101 | |
0e1357e8 | 1102 | if (running_msec < devc->limit_msec && numchunks < 32767) |
6868626b | 1103 | /* Still capturing. */ |
6aac7737 | 1104 | return TRUE; |
6aac7737 | 1105 | |
6868626b BV |
1106 | /* Stop acquisition. */ |
1107 | sigma_set_register(WRITE_MODE, 0x11, devc); | |
28a35d8a | 1108 | |
6868626b BV |
1109 | /* Set SDRAM Read Enable. */ |
1110 | sigma_set_register(WRITE_MODE, 0x02, devc); | |
28a35d8a | 1111 | |
6868626b BV |
1112 | /* Get the current position. */ |
1113 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); | |
28a35d8a | 1114 | |
6868626b BV |
1115 | /* Check if trigger has fired. */ |
1116 | modestatus = sigma_get_register(READ_MODE, devc); | |
1117 | if (modestatus & 0x20) | |
1118 | devc->state.triggerchunk = devc->state.triggerpos / 512; | |
1119 | else | |
1120 | devc->state.triggerchunk = -1; | |
28a35d8a | 1121 | |
6868626b BV |
1122 | /* Transfer captured data from device. */ |
1123 | download_capture(sdi); | |
88c51afe | 1124 | |
6868626b BV |
1125 | /* All done. */ |
1126 | packet.type = SR_DF_END; | |
1127 | sr_session_send(sdi, &packet); | |
88c51afe | 1128 | |
6868626b | 1129 | dev_acquisition_stop(sdi, sdi); |
28a35d8a HE |
1130 | } |
1131 | ||
28a35d8a HE |
1132 | return TRUE; |
1133 | } | |
1134 | ||
c53d793f HE |
1135 | /* Build a LUT entry used by the trigger functions. */ |
1136 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1137 | { |
1138 | int i, j, k, bit; | |
1139 | ||
ba7dd8bb | 1140 | /* For each quad channel. */ |
ee492173 | 1141 | for (i = 0; i < 4; ++i) { |
c53d793f | 1142 | entry[i] = 0xffff; |
ee492173 | 1143 | |
f758d074 | 1144 | /* For each bit in LUT. */ |
ee492173 HE |
1145 | for (j = 0; j < 16; ++j) |
1146 | ||
ba7dd8bb | 1147 | /* For each channel in quad. */ |
ee492173 HE |
1148 | for (k = 0; k < 4; ++k) { |
1149 | bit = 1 << (i * 4 + k); | |
1150 | ||
c53d793f HE |
1151 | /* Set bit in entry */ |
1152 | if ((mask & bit) && | |
1153 | ((!(value & bit)) != | |
4ae1f451 | 1154 | (!(j & (1 << k))))) |
c53d793f | 1155 | entry[i] &= ~(1 << j); |
ee492173 HE |
1156 | } |
1157 | } | |
c53d793f | 1158 | } |
ee492173 | 1159 | |
c53d793f HE |
1160 | /* Add a logical function to LUT mask. */ |
1161 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1162 | int index, int neg, uint16_t *mask) | |
1163 | { | |
1164 | int i, j; | |
1165 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1166 | ||
1167 | memset(x, 0, 4 * sizeof(int)); | |
1168 | ||
1169 | /* Trigger detect condition. */ | |
1170 | switch (oper) { | |
1171 | case OP_LEVEL: | |
1172 | x[0][1] = 1; | |
1173 | x[1][1] = 1; | |
1174 | break; | |
1175 | case OP_NOT: | |
1176 | x[0][0] = 1; | |
1177 | x[1][0] = 1; | |
1178 | break; | |
1179 | case OP_RISE: | |
1180 | x[0][1] = 1; | |
1181 | break; | |
1182 | case OP_FALL: | |
1183 | x[1][0] = 1; | |
1184 | break; | |
1185 | case OP_RISEFALL: | |
1186 | x[0][1] = 1; | |
1187 | x[1][0] = 1; | |
1188 | break; | |
1189 | case OP_NOTRISE: | |
1190 | x[1][1] = 1; | |
1191 | x[0][0] = 1; | |
1192 | x[1][0] = 1; | |
1193 | break; | |
1194 | case OP_NOTFALL: | |
1195 | x[1][1] = 1; | |
1196 | x[0][0] = 1; | |
1197 | x[0][1] = 1; | |
1198 | break; | |
1199 | case OP_NOTRISEFALL: | |
1200 | x[1][1] = 1; | |
1201 | x[0][0] = 1; | |
1202 | break; | |
1203 | } | |
1204 | ||
1205 | /* Transpose if neg is set. */ | |
1206 | if (neg) { | |
ea9cfed7 | 1207 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1208 | for (j = 0; j < 2; ++j) { |
1209 | tmp = x[i][j]; | |
1210 | x[i][j] = x[1-i][1-j]; | |
1211 | x[1-i][1-j] = tmp; | |
1212 | } | |
ea9cfed7 | 1213 | } |
c53d793f HE |
1214 | } |
1215 | ||
1216 | /* Update mask with function. */ | |
1217 | for (i = 0; i < 16; ++i) { | |
1218 | a = (i >> (2 * index + 0)) & 1; | |
1219 | b = (i >> (2 * index + 1)) & 1; | |
1220 | ||
1221 | aset = (*mask >> i) & 1; | |
1222 | bset = x[b][a]; | |
1223 | ||
1224 | if (func == FUNC_AND || func == FUNC_NAND) | |
1225 | rset = aset & bset; | |
1226 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1227 | rset = aset | bset; | |
1228 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1229 | rset = aset ^ bset; | |
1230 | ||
1231 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1232 | rset = !rset; | |
1233 | ||
1234 | *mask &= ~(1 << i); | |
1235 | ||
1236 | if (rset) | |
1237 | *mask |= 1 << i; | |
1238 | } | |
1239 | } | |
1240 | ||
1241 | /* | |
1242 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1243 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1244 | * set at any time, but a full mask and value can be set (0/1). | |
1245 | */ | |
0e1357e8 | 1246 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1247 | { |
1248 | int i,j; | |
4ae1f451 | 1249 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1250 | |
1251 | memset(lut, 0, sizeof(struct triggerlut)); | |
1252 | ||
1253 | /* Contant for simple triggers. */ | |
1254 | lut->m4 = 0xa000; | |
1255 | ||
1256 | /* Value/mask trigger support. */ | |
0e1357e8 | 1257 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1258 | lut->m2d); |
c53d793f HE |
1259 | |
1260 | /* Rise/fall trigger support. */ | |
1261 | for (i = 0, j = 0; i < 16; ++i) { | |
0e1357e8 BV |
1262 | if (devc->trigger.risingmask & (1 << i) || |
1263 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1264 | masks[j++] = 1 << i; |
1265 | } | |
1266 | ||
1267 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1268 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1269 | ||
1270 | /* Add glue logic */ | |
1271 | if (masks[0] || masks[1]) { | |
1272 | /* Transition trigger. */ | |
0e1357e8 | 1273 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1274 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1275 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1276 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1277 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1278 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1279 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1280 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1281 | } else { | |
1282 | /* Only value/mask trigger. */ | |
1283 | lut->m3 = 0xffff; | |
1284 | } | |
ee492173 | 1285 | |
c53d793f | 1286 | /* Triggertype: event. */ |
ee492173 HE |
1287 | lut->params.selres = 3; |
1288 | ||
e46b8fb1 | 1289 | return SR_OK; |
ee492173 HE |
1290 | } |
1291 | ||
6078d2c9 | 1292 | static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1293 | { |
0e1357e8 | 1294 | struct dev_context *devc; |
9ddb2a12 | 1295 | struct clockselect_50 clockselect; |
82957b65 | 1296 | int frac, triggerpin, ret; |
f4abaa9f | 1297 | uint8_t triggerselect = 0; |
57bbf56b | 1298 | struct triggerinout triggerinout_conf; |
ee492173 | 1299 | struct triggerlut lut; |
28a35d8a | 1300 | |
e73ffd42 BV |
1301 | if (sdi->status != SR_ST_ACTIVE) |
1302 | return SR_ERR_DEV_CLOSED; | |
1303 | ||
0e1357e8 | 1304 | devc = sdi->priv; |
28a35d8a | 1305 | |
ba7dd8bb UH |
1306 | if (configure_channels(sdi) != SR_OK) { |
1307 | sr_err("Failed to configure channels."); | |
014359e3 BV |
1308 | return SR_ERR; |
1309 | } | |
1310 | ||
ea9cfed7 | 1311 | /* If the samplerate has not been set, default to 200 kHz. */ |
0e1357e8 | 1312 | if (devc->cur_firmware == -1) { |
82957b65 UH |
1313 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1314 | return ret; | |
1315 | } | |
e8397563 | 1316 | |
eec5275e | 1317 | /* Enter trigger programming mode. */ |
0e1357e8 | 1318 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); |
28a35d8a | 1319 | |
eec5275e | 1320 | /* 100 and 200 MHz mode. */ |
0e1357e8 BV |
1321 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
1322 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
57bbf56b | 1323 | |
a42aec7f HE |
1324 | /* Find which pin to trigger on from mask. */ |
1325 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
0e1357e8 | 1326 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & |
a42aec7f HE |
1327 | (1 << triggerpin)) |
1328 | break; | |
1329 | ||
1330 | /* Set trigger pin and light LED on trigger. */ | |
1331 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1332 | ||
1333 | /* Default rising edge. */ | |
0e1357e8 | 1334 | if (devc->trigger.fallingmask) |
a42aec7f | 1335 | triggerselect |= 1 << 3; |
57bbf56b | 1336 | |
eec5275e | 1337 | /* All other modes. */ |
0e1357e8 BV |
1338 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { |
1339 | build_basic_trigger(&lut, devc); | |
ee492173 | 1340 | |
0e1357e8 | 1341 | sigma_write_trigger_lut(&lut, devc); |
57bbf56b HE |
1342 | |
1343 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1344 | } | |
1345 | ||
eec5275e | 1346 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1347 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1348 | triggerinout_conf.trgout_bytrigger = 1; | |
1349 | triggerinout_conf.trgout_enable = 1; | |
1350 | ||
28a35d8a | 1351 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1352 | (uint8_t *) &triggerinout_conf, |
0e1357e8 | 1353 | sizeof(struct triggerinout), devc); |
28a35d8a | 1354 | |
eec5275e | 1355 | /* Go back to normal mode. */ |
0e1357e8 | 1356 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); |
28a35d8a | 1357 | |
edca2c5c | 1358 | /* Set clock select register. */ |
0e1357e8 | 1359 | if (devc->cur_samplerate == SR_MHZ(200)) |
ba7dd8bb | 1360 | /* Enable 4 channels. */ |
0e1357e8 BV |
1361 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); |
1362 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
ba7dd8bb | 1363 | /* Enable 8 channels. */ |
0e1357e8 | 1364 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); |
edca2c5c HE |
1365 | else { |
1366 | /* | |
9ddb2a12 | 1367 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1368 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1369 | */ |
0e1357e8 | 1370 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; |
edca2c5c | 1371 | |
9ddb2a12 UH |
1372 | clockselect.async = 0; |
1373 | clockselect.fraction = frac; | |
ba7dd8bb | 1374 | clockselect.disabled_channels = 0; |
edca2c5c HE |
1375 | |
1376 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1377 | (uint8_t *) &clockselect, |
0e1357e8 | 1378 | sizeof(clockselect), devc); |
edca2c5c HE |
1379 | } |
1380 | ||
fefa1800 | 1381 | /* Setup maximum post trigger time. */ |
99965709 | 1382 | sigma_set_register(WRITE_POST_TRIGGER, |
0e1357e8 | 1383 | (devc->capture_ratio * 255) / 100, devc); |
28a35d8a | 1384 | |
eec5275e | 1385 | /* Start acqusition. */ |
0e1357e8 BV |
1386 | gettimeofday(&devc->start_tv, 0); |
1387 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
99965709 | 1388 | |
3e9b7f9c | 1389 | devc->cb_data = cb_data; |
28a35d8a | 1390 | |
3c36c403 | 1391 | /* Send header packet to the session bus. */ |
29a27196 | 1392 | std_session_send_df_header(cb_data, LOG_PREFIX); |
f366e86c | 1393 | |
f366e86c | 1394 | /* Add capture source. */ |
3ffb6964 | 1395 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); |
f366e86c | 1396 | |
0e1357e8 | 1397 | devc->state.state = SIGMA_CAPTURE; |
6aac7737 | 1398 | |
e46b8fb1 | 1399 | return SR_OK; |
28a35d8a HE |
1400 | } |
1401 | ||
6078d2c9 | 1402 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1403 | { |
0e1357e8 | 1404 | struct dev_context *devc; |
6aac7737 | 1405 | |
3cd3a20b | 1406 | (void)cb_data; |
28a35d8a | 1407 | |
6868626b BV |
1408 | devc = sdi->priv; |
1409 | devc->state.state = SIGMA_IDLE; | |
6aac7737 | 1410 | |
6868626b | 1411 | sr_source_remove(0); |
3010f21c UH |
1412 | |
1413 | return SR_OK; | |
28a35d8a HE |
1414 | } |
1415 | ||
c09f0b57 | 1416 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 | 1417 | .name = "asix-sigma", |
6352d030 | 1418 | .longname = "ASIX SIGMA/SIGMA2", |
e519ba86 | 1419 | .api_version = 1, |
6078d2c9 UH |
1420 | .init = init, |
1421 | .cleanup = cleanup, | |
1422 | .scan = scan, | |
1423 | .dev_list = dev_list, | |
3b412e3a | 1424 | .dev_clear = dev_clear, |
035a1078 BV |
1425 | .config_get = config_get, |
1426 | .config_set = config_set, | |
a1c743fc | 1427 | .config_list = config_list, |
6078d2c9 UH |
1428 | .dev_open = dev_open, |
1429 | .dev_close = dev_close, | |
1430 | .dev_acquisition_start = dev_acquisition_start, | |
1431 | .dev_acquisition_stop = dev_acquisition_stop, | |
0e1357e8 | 1432 | .priv = NULL, |
28a35d8a | 1433 | }; |