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Commit | Line | Data |
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28a35d8a | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
28a35d8a | 3 | * |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
45c59c8b BV |
30 | #include "libsigrok.h" |
31 | #include "libsigrok-internal.h" | |
28a35d8a HE |
32 | #include "asix-sigma.h" |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
c50277a6 | 39 | #define TRIGGER_TYPE "rf10" |
28a35d8a | 40 | |
ed300b9f | 41 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; |
a873c594 | 42 | static struct sr_dev_driver *di = &asix_sigma_driver_info; |
6078d2c9 | 43 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data); |
28a35d8a | 44 | |
b1648dea MV |
45 | /* |
46 | * The ASIX Sigma supports arbitrary integer frequency divider in | |
47 | * the 50MHz mode. The divider is in range 1...256 , allowing for | |
48 | * very precise sampling rate selection. This driver supports only | |
49 | * a subset of the sampling rates. | |
50 | */ | |
2c9c0df8 | 51 | static const uint64_t samplerates[] = { |
b1648dea MV |
52 | SR_KHZ(200), /* div=250 */ |
53 | SR_KHZ(250), /* div=200 */ | |
54 | SR_KHZ(500), /* div=100 */ | |
55 | SR_MHZ(1), /* div=50 */ | |
56 | SR_MHZ(5), /* div=10 */ | |
57 | SR_MHZ(10), /* div=5 */ | |
58 | SR_MHZ(25), /* div=2 */ | |
59 | SR_MHZ(50), /* div=1 */ | |
60 | SR_MHZ(100), /* Special FW needed */ | |
61 | SR_MHZ(200), /* Special FW needed */ | |
28a35d8a HE |
62 | }; |
63 | ||
d261dbbf | 64 | /* |
ba7dd8bb | 65 | * Channel numbers seem to go from 1-16, according to this image: |
d261dbbf UH |
66 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg |
67 | * (the cable has two additional GND pins, and a TI and TO pin) | |
68 | */ | |
790c7ccc | 69 | static const char *channel_names[] = { |
78693401 UH |
70 | "1", "2", "3", "4", "5", "6", "7", "8", |
71 | "9", "10", "11", "12", "13", "14", "15", "16", | |
464d12c7 KS |
72 | }; |
73 | ||
2c9c0df8 | 74 | static const int32_t hwcaps[] = { |
1953564a BV |
75 | SR_CONF_LOGIC_ANALYZER, |
76 | SR_CONF_SAMPLERATE, | |
38d32464 | 77 | SR_CONF_TRIGGER_TYPE, |
1953564a | 78 | SR_CONF_CAPTURE_RATIO, |
1953564a | 79 | SR_CONF_LIMIT_MSEC, |
28a35d8a HE |
80 | }; |
81 | ||
499b17e9 MV |
82 | static const char *sigma_firmware_files[] = { |
83 | /* 50 MHz, supports 8 bit fractions */ | |
84 | FIRMWARE_DIR "/asix-sigma-50.fw", | |
85 | /* 100 MHz */ | |
86 | FIRMWARE_DIR "/asix-sigma-100.fw", | |
87 | /* 200 MHz */ | |
88 | FIRMWARE_DIR "/asix-sigma-200.fw", | |
89 | /* Synchronous clock from pin */ | |
90 | FIRMWARE_DIR "/asix-sigma-50sync.fw", | |
91 | /* Frequency counter */ | |
92 | FIRMWARE_DIR "/asix-sigma-phasor.fw", | |
f6564c8d HE |
93 | }; |
94 | ||
0e1357e8 | 95 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
96 | { |
97 | int ret; | |
fefa1800 | 98 | |
0e1357e8 | 99 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 100 | if (ret < 0) { |
47f4f073 | 101 | sr_err("ftdi_read_data failed: %s", |
0e1357e8 | 102 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
103 | } |
104 | ||
105 | return ret; | |
106 | } | |
107 | ||
0e1357e8 | 108 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
109 | { |
110 | int ret; | |
fefa1800 | 111 | |
0e1357e8 | 112 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 113 | if (ret < 0) { |
47f4f073 | 114 | sr_err("ftdi_write_data failed: %s", |
0e1357e8 | 115 | ftdi_get_error_string(&devc->ftdic)); |
fefa1800 | 116 | } else if ((size_t) ret != size) { |
47f4f073 | 117 | sr_err("ftdi_write_data did not complete write."); |
28a35d8a HE |
118 | } |
119 | ||
120 | return ret; | |
121 | } | |
122 | ||
99965709 | 123 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 124 | struct dev_context *devc) |
28a35d8a HE |
125 | { |
126 | size_t i; | |
127 | uint8_t buf[len + 2]; | |
128 | int idx = 0; | |
129 | ||
130 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
131 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
132 | ||
fefa1800 | 133 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
134 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
135 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
136 | } | |
137 | ||
0e1357e8 | 138 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
139 | } |
140 | ||
0e1357e8 | 141 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 142 | { |
0e1357e8 | 143 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
144 | } |
145 | ||
99965709 | 146 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 147 | struct dev_context *devc) |
28a35d8a HE |
148 | { |
149 | uint8_t buf[3]; | |
fefa1800 | 150 | |
28a35d8a HE |
151 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
152 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
153 | buf[2] = REG_READ_ADDR; |
154 | ||
0e1357e8 | 155 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 156 | |
0e1357e8 | 157 | return sigma_read(data, len, devc); |
28a35d8a HE |
158 | } |
159 | ||
0e1357e8 | 160 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) |
28a35d8a HE |
161 | { |
162 | uint8_t value; | |
fefa1800 | 163 | |
0e1357e8 | 164 | if (1 != sigma_read_register(reg, &value, 1, devc)) { |
47f4f073 | 165 | sr_err("sigma_get_register: 1 byte expected"); |
28a35d8a HE |
166 | return 0; |
167 | } | |
168 | ||
169 | return value; | |
170 | } | |
171 | ||
99965709 | 172 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 173 | struct dev_context *devc) |
28a35d8a HE |
174 | { |
175 | uint8_t buf[] = { | |
176 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
177 | ||
178 | REG_READ_ADDR | NEXT_REG, | |
179 | REG_READ_ADDR | NEXT_REG, | |
180 | REG_READ_ADDR | NEXT_REG, | |
181 | REG_READ_ADDR | NEXT_REG, | |
182 | REG_READ_ADDR | NEXT_REG, | |
183 | REG_READ_ADDR | NEXT_REG, | |
184 | }; | |
28a35d8a HE |
185 | uint8_t result[6]; |
186 | ||
0e1357e8 | 187 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 188 | |
0e1357e8 | 189 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
190 | |
191 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
192 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
193 | ||
57bbf56b HE |
194 | /* Not really sure why this must be done, but according to spec. */ |
195 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
196 | stoppos -= 64; | |
197 | ||
198 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
199 | triggerpos -= 64; | |
200 | ||
28a35d8a HE |
201 | return 1; |
202 | } | |
203 | ||
99965709 | 204 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 205 | uint8_t *data, struct dev_context *devc) |
28a35d8a HE |
206 | { |
207 | size_t i; | |
208 | uint8_t buf[4096]; | |
209 | int idx = 0; | |
210 | ||
fefa1800 | 211 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
212 | buf[0] = startchunk >> 8; |
213 | buf[1] = startchunk & 0xff; | |
0e1357e8 | 214 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); |
28a35d8a | 215 | |
fefa1800 | 216 | /* Read the DRAM. */ |
28a35d8a HE |
217 | buf[idx++] = REG_DRAM_BLOCK; |
218 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
219 | ||
220 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
221 | /* Alternate bit to copy from DRAM to cache. */ |
222 | if (i != (numchunks - 1)) | |
223 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
224 | |
225 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
226 | ||
fefa1800 | 227 | if (i != (numchunks - 1)) |
28a35d8a HE |
228 | buf[idx++] = REG_DRAM_WAIT_ACK; |
229 | } | |
230 | ||
0e1357e8 | 231 | sigma_write(buf, idx, devc); |
28a35d8a | 232 | |
0e1357e8 | 233 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); |
28a35d8a HE |
234 | } |
235 | ||
4ae1f451 | 236 | /* Upload trigger look-up tables to Sigma. */ |
0e1357e8 | 237 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
238 | { |
239 | int i; | |
240 | uint8_t tmp[2]; | |
241 | uint16_t bit; | |
242 | ||
243 | /* Transpose the table and send to Sigma. */ | |
244 | for (i = 0; i < 16; ++i) { | |
245 | bit = 1 << i; | |
246 | ||
247 | tmp[0] = tmp[1] = 0; | |
248 | ||
249 | if (lut->m2d[0] & bit) | |
250 | tmp[0] |= 0x01; | |
251 | if (lut->m2d[1] & bit) | |
252 | tmp[0] |= 0x02; | |
253 | if (lut->m2d[2] & bit) | |
254 | tmp[0] |= 0x04; | |
255 | if (lut->m2d[3] & bit) | |
256 | tmp[0] |= 0x08; | |
257 | ||
258 | if (lut->m3 & bit) | |
259 | tmp[0] |= 0x10; | |
260 | if (lut->m3s & bit) | |
261 | tmp[0] |= 0x20; | |
262 | if (lut->m4 & bit) | |
263 | tmp[0] |= 0x40; | |
264 | ||
265 | if (lut->m0d[0] & bit) | |
266 | tmp[1] |= 0x01; | |
267 | if (lut->m0d[1] & bit) | |
268 | tmp[1] |= 0x02; | |
269 | if (lut->m0d[2] & bit) | |
270 | tmp[1] |= 0x04; | |
271 | if (lut->m0d[3] & bit) | |
272 | tmp[1] |= 0x08; | |
273 | ||
274 | if (lut->m1d[0] & bit) | |
275 | tmp[1] |= 0x10; | |
276 | if (lut->m1d[1] & bit) | |
277 | tmp[1] |= 0x20; | |
278 | if (lut->m1d[2] & bit) | |
279 | tmp[1] |= 0x40; | |
280 | if (lut->m1d[3] & bit) | |
281 | tmp[1] |= 0x80; | |
282 | ||
99965709 | 283 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
0e1357e8 BV |
284 | devc); |
285 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
ee492173 HE |
286 | } |
287 | ||
288 | /* Send the parameters */ | |
289 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
0e1357e8 | 290 | sizeof(lut->params), devc); |
ee492173 | 291 | |
e46b8fb1 | 292 | return SR_OK; |
ee492173 HE |
293 | } |
294 | ||
3678cf73 | 295 | static void clear_helper(void *priv) |
0448d110 | 296 | { |
0e1357e8 | 297 | struct dev_context *devc; |
ce4d26dd | 298 | |
3678cf73 | 299 | devc = priv; |
0e1357e8 | 300 | |
3678cf73 UH |
301 | ftdi_deinit(&devc->ftdic); |
302 | } | |
0448d110 | 303 | |
3b412e3a | 304 | static int dev_clear(void) |
3678cf73 UH |
305 | { |
306 | return std_dev_clear(di, clear_helper); | |
0448d110 BV |
307 | } |
308 | ||
6078d2c9 | 309 | static int init(struct sr_context *sr_ctx) |
61136ea6 | 310 | { |
f6beaac5 | 311 | return std_init(sr_ctx, di, LOG_PREFIX); |
61136ea6 BV |
312 | } |
313 | ||
6078d2c9 | 314 | static GSList *scan(GSList *options) |
28a35d8a | 315 | { |
d68e2d1a | 316 | struct sr_dev_inst *sdi; |
ba7dd8bb | 317 | struct sr_channel *ch; |
0e1357e8 BV |
318 | struct drv_context *drvc; |
319 | struct dev_context *devc; | |
0448d110 | 320 | GSList *devices; |
e3fff420 HE |
321 | struct ftdi_device_list *devlist; |
322 | char serial_txt[10]; | |
323 | uint32_t serial; | |
790c7ccc MV |
324 | int ret; |
325 | unsigned int i; | |
28a35d8a | 326 | |
0448d110 | 327 | (void)options; |
64d33dc2 | 328 | |
a873c594 | 329 | drvc = di->priv; |
4b97c74e | 330 | |
0448d110 | 331 | devices = NULL; |
4b97c74e | 332 | |
0e1357e8 | 333 | if (!(devc = g_try_malloc(sizeof(struct dev_context)))) { |
47f4f073 | 334 | sr_err("%s: devc malloc failed", __func__); |
0448d110 | 335 | return NULL; |
b53738ba | 336 | } |
99965709 | 337 | |
0e1357e8 | 338 | ftdi_init(&devc->ftdic); |
28a35d8a | 339 | |
fefa1800 | 340 | /* Look for SIGMAs. */ |
e3fff420 | 341 | |
0e1357e8 | 342 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, |
eec944c5 BV |
343 | USB_VENDOR, USB_PRODUCT)) <= 0) { |
344 | if (ret < 0) | |
345 | sr_err("ftdi_usb_find_all(): %d", ret); | |
99965709 | 346 | goto free; |
eec944c5 | 347 | } |
99965709 | 348 | |
e3fff420 | 349 | /* Make sure it's a version 1 or 2 SIGMA. */ |
0e1357e8 | 350 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, |
6352d030 | 351 | serial_txt, sizeof(serial_txt)); |
e3fff420 HE |
352 | sscanf(serial_txt, "%x", &serial); |
353 | ||
6352d030 | 354 | if (serial < 0xa6010000 || serial > 0xa602ffff) { |
47f4f073 UH |
355 | sr_err("Only SIGMA and SIGMA2 are supported " |
356 | "in this version of libsigrok."); | |
e3fff420 HE |
357 | goto free; |
358 | } | |
359 | ||
360 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
361 | ||
23b886bc | 362 | devc->cur_samplerate = samplerates[0]; |
0e1357e8 BV |
363 | devc->period_ps = 0; |
364 | devc->limit_msec = 0; | |
365 | devc->cur_firmware = -1; | |
ba7dd8bb | 366 | devc->num_channels = 0; |
0e1357e8 BV |
367 | devc->samples_per_event = 0; |
368 | devc->capture_ratio = 50; | |
369 | devc->use_triggers = 0; | |
28a35d8a | 370 | |
fefa1800 | 371 | /* Register SIGMA device. */ |
d68e2d1a | 372 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
55f98c65 | 373 | USB_MODEL_NAME, NULL))) { |
47f4f073 | 374 | sr_err("%s: sdi was NULL", __func__); |
99965709 | 375 | goto free; |
d68e2d1a | 376 | } |
a873c594 | 377 | sdi->driver = di; |
87ca93c5 | 378 | |
790c7ccc MV |
379 | for (i = 0; i < ARRAY_SIZE(channel_names); i++) { |
380 | ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE, | |
381 | channel_names[i]); | |
382 | if (!ch) | |
87ca93c5 | 383 | return NULL; |
ba7dd8bb | 384 | sdi->channels = g_slist_append(sdi->channels, ch); |
87ca93c5 BV |
385 | } |
386 | ||
0448d110 | 387 | devices = g_slist_append(devices, sdi); |
0e1357e8 BV |
388 | drvc->instances = g_slist_append(drvc->instances, sdi); |
389 | sdi->priv = devc; | |
28a35d8a | 390 | |
fefa1800 | 391 | /* We will open the device again when we need it. */ |
e3fff420 | 392 | ftdi_list_free(&devlist); |
28a35d8a | 393 | |
0448d110 | 394 | return devices; |
ea9cfed7 | 395 | |
99965709 | 396 | free: |
0e1357e8 BV |
397 | ftdi_deinit(&devc->ftdic); |
398 | g_free(devc); | |
0448d110 | 399 | return NULL; |
28a35d8a HE |
400 | } |
401 | ||
6078d2c9 | 402 | static GSList *dev_list(void) |
811deee4 | 403 | { |
0e94d524 | 404 | return ((struct drv_context *)(di->priv))->instances; |
811deee4 BV |
405 | } |
406 | ||
d5fa188a MV |
407 | /* |
408 | * Configure the FPGA for bitbang mode. | |
409 | * This sequence is documented in section 2. of the ASIX Sigma programming | |
410 | * manual. This sequence is necessary to configure the FPGA in the Sigma | |
411 | * into Bitbang mode, in which it can be programmed with the firmware. | |
412 | */ | |
413 | static int sigma_fpga_init_bitbang(struct dev_context *devc) | |
414 | { | |
415 | uint8_t suicide[] = { | |
416 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
417 | }; | |
418 | uint8_t init_array[] = { | |
419 | 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, | |
420 | 0x01, 0x01, | |
421 | }; | |
422 | int i, ret, timeout = 10000; | |
423 | uint8_t data; | |
424 | ||
425 | /* Section 2. part 1), do the FPGA suicide. */ | |
426 | sigma_write(suicide, sizeof(suicide), devc); | |
427 | sigma_write(suicide, sizeof(suicide), devc); | |
428 | sigma_write(suicide, sizeof(suicide), devc); | |
429 | sigma_write(suicide, sizeof(suicide), devc); | |
430 | ||
431 | /* Section 2. part 2), do pulse on D1. */ | |
432 | sigma_write(init_array, sizeof(init_array), devc); | |
433 | ftdi_usb_purge_buffers(&devc->ftdic); | |
434 | ||
435 | /* Wait until the FPGA asserts D6/INIT_B. */ | |
436 | for (i = 0; i < timeout; i++) { | |
437 | ret = sigma_read(&data, 1, devc); | |
438 | if (ret < 0) | |
439 | return ret; | |
440 | /* Test if pin D6 got asserted. */ | |
441 | if (data & (1 << 5)) | |
442 | return 0; | |
443 | /* The D6 was not asserted yet, wait a bit. */ | |
444 | usleep(10000); | |
445 | } | |
446 | ||
447 | return SR_ERR_TIMEOUT; | |
448 | } | |
449 | ||
64fe661b MV |
450 | /* |
451 | * Configure the FPGA for logic-analyzer mode. | |
452 | */ | |
453 | static int sigma_fpga_init_la(struct dev_context *devc) | |
454 | { | |
455 | /* Initialize the logic analyzer mode. */ | |
456 | uint8_t logic_mode_start[] = { | |
011f1091 MV |
457 | REG_ADDR_LOW | (READ_ID & 0xf), |
458 | REG_ADDR_HIGH | (READ_ID >> 8), | |
459 | REG_READ_ADDR, /* Read ID register. */ | |
460 | ||
461 | REG_ADDR_LOW | (WRITE_TEST & 0xf), | |
462 | REG_DATA_LOW | 0x5, | |
463 | REG_DATA_HIGH_WRITE | 0x5, | |
464 | REG_READ_ADDR, /* Read scratch register. */ | |
465 | ||
466 | REG_DATA_LOW | 0xa, | |
467 | REG_DATA_HIGH_WRITE | 0xa, | |
468 | REG_READ_ADDR, /* Read scratch register. */ | |
469 | ||
470 | REG_ADDR_LOW | (WRITE_MODE & 0xf), | |
471 | REG_DATA_LOW | 0x0, | |
472 | REG_DATA_HIGH_WRITE | 0x8, | |
64fe661b MV |
473 | }; |
474 | ||
475 | uint8_t result[3]; | |
476 | int ret; | |
477 | ||
478 | /* Initialize the logic analyzer mode. */ | |
479 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); | |
480 | ||
011f1091 | 481 | /* Expect a 3 byte reply since we issued three READ requests. */ |
64fe661b MV |
482 | ret = sigma_read(result, 3, devc); |
483 | if (ret != 3) | |
484 | goto err; | |
485 | ||
486 | if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) | |
487 | goto err; | |
488 | ||
489 | return SR_OK; | |
490 | err: | |
491 | sr_err("Configuration failed. Invalid reply received."); | |
492 | return SR_ERR; | |
493 | } | |
494 | ||
a80226bb MV |
495 | /* |
496 | * Read the firmware from a file and transform it into a series of bitbang | |
497 | * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d | |
498 | * by the caller of this function. | |
499 | */ | |
500 | static int sigma_fw_2_bitbang(const char *filename, | |
501 | uint8_t **bb_cmd, gsize *bb_cmd_size) | |
502 | { | |
503 | GMappedFile *file; | |
504 | GError *error; | |
505 | gsize i, file_size, bb_size; | |
506 | gchar *firmware; | |
507 | uint8_t *bb_stream, *bbs; | |
508 | uint32_t imm; | |
509 | int bit, v; | |
510 | int ret = SR_OK; | |
511 | ||
512 | /* | |
513 | * Map the file and make the mapped buffer writable. | |
514 | * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped | |
515 | * will be modified. It will not be modified until someone uses | |
516 | * g_file_set_contents() on it. | |
517 | */ | |
518 | error = NULL; | |
519 | file = g_mapped_file_new(filename, TRUE, &error); | |
520 | g_assert_no_error(error); | |
521 | ||
522 | file_size = g_mapped_file_get_length(file); | |
523 | firmware = g_mapped_file_get_contents(file); | |
524 | g_assert(firmware); | |
525 | ||
526 | /* Weird magic transformation below, I have no idea what it does. */ | |
527 | imm = 0x3f6df2ab; | |
528 | for (i = 0; i < file_size; i++) { | |
529 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
530 | firmware[i] ^= imm & 0xff; | |
531 | } | |
532 | ||
533 | /* | |
534 | * Now that the firmware is "transformed", we will transcribe the | |
535 | * firmware blob into a sequence of toggles of the Dx wires. This | |
536 | * sequence will be fed directly into the Sigma, which must be in | |
537 | * the FPGA bitbang programming mode. | |
538 | */ | |
539 | ||
540 | /* Each bit of firmware is transcribed as two toggles of Dx wires. */ | |
541 | bb_size = file_size * 8 * 2; | |
542 | bb_stream = (uint8_t *)g_try_malloc(bb_size); | |
543 | if (!bb_stream) { | |
544 | sr_err("%s: Failed to allocate bitbang stream", __func__); | |
545 | ret = SR_ERR_MALLOC; | |
546 | goto exit; | |
547 | } | |
548 | ||
549 | bbs = bb_stream; | |
550 | for (i = 0; i < file_size; i++) { | |
551 | for (bit = 7; bit >= 0; bit--) { | |
552 | v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00; | |
553 | *bbs++ = v | 0x01; | |
554 | *bbs++ = v; | |
555 | } | |
556 | } | |
557 | ||
558 | /* The transformation completed successfully, return the result. */ | |
559 | *bb_cmd = bb_stream; | |
560 | *bb_cmd_size = bb_size; | |
561 | ||
562 | exit: | |
563 | g_mapped_file_unref(file); | |
564 | return ret; | |
565 | } | |
566 | ||
0e1357e8 | 567 | static int upload_firmware(int firmware_idx, struct dev_context *devc) |
28a35d8a HE |
568 | { |
569 | int ret; | |
570 | unsigned char *buf; | |
571 | unsigned char pins; | |
572 | size_t buf_size; | |
499b17e9 | 573 | const char *firmware = sigma_firmware_files[firmware_idx]; |
8bbf7627 | 574 | struct ftdi_context *ftdic = &devc->ftdic; |
28a35d8a | 575 | |
fefa1800 | 576 | /* Make sure it's an ASIX SIGMA. */ |
8bbf7627 MV |
577 | ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT, |
578 | USB_DESCRIPTION, NULL); | |
579 | if (ret < 0) { | |
47f4f073 | 580 | sr_err("ftdi_usb_open failed: %s", |
8bbf7627 | 581 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
582 | return 0; |
583 | } | |
584 | ||
8bbf7627 MV |
585 | ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG); |
586 | if (ret < 0) { | |
47f4f073 | 587 | sr_err("ftdi_set_bitmode failed: %s", |
8bbf7627 | 588 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
589 | return 0; |
590 | } | |
591 | ||
fefa1800 | 592 | /* Four times the speed of sigmalogan - Works well. */ |
8bbf7627 MV |
593 | ret = ftdi_set_baudrate(ftdic, 750000); |
594 | if (ret < 0) { | |
47f4f073 | 595 | sr_err("ftdi_set_baudrate failed: %s", |
8bbf7627 | 596 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
597 | return 0; |
598 | } | |
599 | ||
d5fa188a MV |
600 | /* Initialize the FPGA for firmware upload. */ |
601 | ret = sigma_fpga_init_bitbang(devc); | |
602 | if (ret) | |
603 | return ret; | |
28a35d8a | 604 | |
9ddb2a12 | 605 | /* Prepare firmware. */ |
d485d443 | 606 | ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size); |
8bbf7627 | 607 | if (ret != SR_OK) { |
47f4f073 | 608 | sr_err("An error occured while reading the firmware: %s", |
499b17e9 | 609 | firmware); |
b53738ba | 610 | return ret; |
28a35d8a HE |
611 | } |
612 | ||
fefa1800 | 613 | /* Upload firmare. */ |
499b17e9 | 614 | sr_info("Uploading firmware file '%s'.", firmware); |
0e1357e8 | 615 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
616 | |
617 | g_free(buf); | |
618 | ||
8bbf7627 MV |
619 | ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET); |
620 | if (ret < 0) { | |
47f4f073 | 621 | sr_err("ftdi_set_bitmode failed: %s", |
8bbf7627 | 622 | ftdi_get_error_string(ftdic)); |
e46b8fb1 | 623 | return SR_ERR; |
28a35d8a HE |
624 | } |
625 | ||
8bbf7627 | 626 | ftdi_usb_purge_buffers(ftdic); |
28a35d8a | 627 | |
fefa1800 | 628 | /* Discard garbage. */ |
29b66a2e | 629 | while (sigma_read(&pins, 1, devc) == 1) |
28a35d8a HE |
630 | ; |
631 | ||
64fe661b MV |
632 | /* Initialize the FPGA for logic-analyzer mode. */ |
633 | ret = sigma_fpga_init_la(devc); | |
634 | if (ret != SR_OK) | |
635 | return ret; | |
28a35d8a | 636 | |
0e1357e8 | 637 | devc->cur_firmware = firmware_idx; |
f6564c8d | 638 | |
47f4f073 | 639 | sr_info("Firmware uploaded."); |
e3fff420 | 640 | |
e46b8fb1 | 641 | return SR_OK; |
f6564c8d HE |
642 | } |
643 | ||
6078d2c9 | 644 | static int dev_open(struct sr_dev_inst *sdi) |
f6564c8d | 645 | { |
0e1357e8 | 646 | struct dev_context *devc; |
f6564c8d HE |
647 | int ret; |
648 | ||
0e1357e8 | 649 | devc = sdi->priv; |
99965709 | 650 | |
9ddb2a12 | 651 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 652 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
f6564c8d HE |
653 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
654 | ||
47f4f073 | 655 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 656 | ftdi_get_error_string(&devc->ftdic)); |
f6564c8d HE |
657 | |
658 | return 0; | |
659 | } | |
28a35d8a | 660 | |
5a2326a7 | 661 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 662 | |
e46b8fb1 | 663 | return SR_OK; |
f6564c8d HE |
664 | } |
665 | ||
6f4b1868 | 666 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 667 | { |
2c9c0df8 BV |
668 | struct dev_context *devc; |
669 | unsigned int i; | |
670 | int ret; | |
f6564c8d | 671 | |
2c9c0df8 | 672 | devc = sdi->priv; |
f4abaa9f UH |
673 | ret = SR_OK; |
674 | ||
2c9c0df8 BV |
675 | for (i = 0; i < ARRAY_SIZE(samplerates); i++) { |
676 | if (samplerates[i] == samplerate) | |
f6564c8d HE |
677 | break; |
678 | } | |
2c9c0df8 | 679 | if (samplerates[i] == 0) |
e46b8fb1 | 680 | return SR_ERR_SAMPLERATE; |
f6564c8d | 681 | |
59df0c77 | 682 | if (samplerate <= SR_MHZ(50)) { |
0e1357e8 | 683 | ret = upload_firmware(0, devc); |
ba7dd8bb | 684 | devc->num_channels = 16; |
e8397563 | 685 | } |
59df0c77 | 686 | if (samplerate == SR_MHZ(100)) { |
0e1357e8 | 687 | ret = upload_firmware(1, devc); |
ba7dd8bb | 688 | devc->num_channels = 8; |
f78898e9 | 689 | } |
59df0c77 | 690 | else if (samplerate == SR_MHZ(200)) { |
0e1357e8 | 691 | ret = upload_firmware(2, devc); |
ba7dd8bb | 692 | devc->num_channels = 4; |
f78898e9 | 693 | } |
f6564c8d | 694 | |
0e1357e8 | 695 | devc->cur_samplerate = samplerate; |
5edc02c7 | 696 | devc->period_ps = 1000000000000ULL / samplerate; |
ba7dd8bb | 697 | devc->samples_per_event = 16 / devc->num_channels; |
0e1357e8 | 698 | devc->state.state = SIGMA_IDLE; |
f6564c8d | 699 | |
e8397563 | 700 | return ret; |
28a35d8a HE |
701 | } |
702 | ||
c53d793f HE |
703 | /* |
704 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
705 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
ba7dd8bb | 706 | * in addition to value/mask trigger for any number of channels. |
c53d793f HE |
707 | * |
708 | * The Sigma supports complex triggers using boolean expressions, but this | |
709 | * has not been implemented yet. | |
710 | */ | |
ba7dd8bb | 711 | static int configure_channels(const struct sr_dev_inst *sdi) |
57bbf56b | 712 | { |
0e1357e8 | 713 | struct dev_context *devc = sdi->priv; |
ba7dd8bb | 714 | const struct sr_channel *ch; |
1b79df2f | 715 | const GSList *l; |
57bbf56b | 716 | int trigger_set = 0; |
ba7dd8bb | 717 | int channelbit; |
57bbf56b | 718 | |
0e1357e8 | 719 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 720 | |
ba7dd8bb UH |
721 | for (l = sdi->channels; l; l = l->next) { |
722 | ch = (struct sr_channel *)l->data; | |
723 | channelbit = 1 << (ch->index); | |
57bbf56b | 724 | |
ba7dd8bb | 725 | if (!ch->enabled || !ch->trigger) |
57bbf56b HE |
726 | continue; |
727 | ||
0e1357e8 | 728 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 729 | /* Fast trigger support. */ |
ee492173 | 730 | if (trigger_set) { |
47f4f073 UH |
731 | sr_err("Only a single pin trigger in 100 and " |
732 | "200MHz mode is supported."); | |
e46b8fb1 | 733 | return SR_ERR; |
ee492173 | 734 | } |
ba7dd8bb UH |
735 | if (ch->trigger[0] == 'f') |
736 | devc->trigger.fallingmask |= channelbit; | |
737 | else if (ch->trigger[0] == 'r') | |
738 | devc->trigger.risingmask |= channelbit; | |
ee492173 | 739 | else { |
47f4f073 UH |
740 | sr_err("Only rising/falling trigger in 100 " |
741 | "and 200MHz mode is supported."); | |
e46b8fb1 | 742 | return SR_ERR; |
ee492173 | 743 | } |
57bbf56b | 744 | |
c53d793f | 745 | ++trigger_set; |
ee492173 | 746 | } else { |
c53d793f | 747 | /* Simple trigger support (event). */ |
ba7dd8bb UH |
748 | if (ch->trigger[0] == '1') { |
749 | devc->trigger.simplevalue |= channelbit; | |
750 | devc->trigger.simplemask |= channelbit; | |
c53d793f | 751 | } |
ba7dd8bb UH |
752 | else if (ch->trigger[0] == '0') { |
753 | devc->trigger.simplevalue &= ~channelbit; | |
754 | devc->trigger.simplemask |= channelbit; | |
c53d793f | 755 | } |
ba7dd8bb UH |
756 | else if (ch->trigger[0] == 'f') { |
757 | devc->trigger.fallingmask |= channelbit; | |
c53d793f HE |
758 | ++trigger_set; |
759 | } | |
ba7dd8bb UH |
760 | else if (ch->trigger[0] == 'r') { |
761 | devc->trigger.risingmask |= channelbit; | |
c53d793f HE |
762 | ++trigger_set; |
763 | } | |
ee492173 | 764 | |
ea9cfed7 UH |
765 | /* |
766 | * Actually, Sigma supports 2 rising/falling triggers, | |
767 | * but they are ORed and the current trigger syntax | |
768 | * does not permit ORed triggers. | |
769 | */ | |
98b8cbc1 | 770 | if (trigger_set > 1) { |
47f4f073 UH |
771 | sr_err("Only 1 rising/falling trigger " |
772 | "is supported."); | |
e46b8fb1 | 773 | return SR_ERR; |
ee492173 | 774 | } |
ee492173 | 775 | } |
5b5ea7c6 HE |
776 | |
777 | if (trigger_set) | |
0e1357e8 | 778 | devc->use_triggers = 1; |
57bbf56b HE |
779 | } |
780 | ||
e46b8fb1 | 781 | return SR_OK; |
57bbf56b HE |
782 | } |
783 | ||
6078d2c9 | 784 | static int dev_close(struct sr_dev_inst *sdi) |
28a35d8a | 785 | { |
0e1357e8 | 786 | struct dev_context *devc; |
28a35d8a | 787 | |
961009b0 | 788 | devc = sdi->priv; |
697785d1 UH |
789 | |
790 | /* TODO */ | |
791 | if (sdi->status == SR_ST_ACTIVE) | |
0e1357e8 | 792 | ftdi_usb_close(&devc->ftdic); |
697785d1 UH |
793 | |
794 | sdi->status = SR_ST_INACTIVE; | |
795 | ||
796 | return SR_OK; | |
28a35d8a HE |
797 | } |
798 | ||
6078d2c9 | 799 | static int cleanup(void) |
28a35d8a | 800 | { |
3b412e3a | 801 | return dev_clear(); |
28a35d8a HE |
802 | } |
803 | ||
8f996b89 | 804 | static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi, |
53b4680f | 805 | const struct sr_channel_group *cg) |
28a35d8a | 806 | { |
0e1357e8 | 807 | struct dev_context *devc; |
99965709 | 808 | |
53b4680f | 809 | (void)cg; |
8f996b89 | 810 | |
fb2e6de7 BV |
811 | if (!sdi) |
812 | return SR_ERR; | |
813 | devc = sdi->priv; | |
814 | ||
035a1078 | 815 | switch (id) { |
123e1313 | 816 | case SR_CONF_SAMPLERATE: |
fb2e6de7 BV |
817 | *data = g_variant_new_uint64(devc->cur_samplerate); |
818 | break; | |
819 | case SR_CONF_LIMIT_MSEC: | |
820 | *data = g_variant_new_uint64(devc->limit_msec); | |
821 | break; | |
822 | case SR_CONF_CAPTURE_RATIO: | |
823 | *data = g_variant_new_uint64(devc->capture_ratio); | |
28a35d8a | 824 | break; |
d7bbecfd | 825 | default: |
bd6fbf62 | 826 | return SR_ERR_NA; |
28a35d8a HE |
827 | } |
828 | ||
41479605 | 829 | return SR_OK; |
28a35d8a HE |
830 | } |
831 | ||
8f996b89 | 832 | static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi, |
53b4680f | 833 | const struct sr_channel_group *cg) |
28a35d8a | 834 | { |
0e1357e8 | 835 | struct dev_context *devc; |
6868626b | 836 | uint64_t num_samples; |
5fc01191 | 837 | int ret = 0; |
f6564c8d | 838 | |
53b4680f | 839 | (void)cg; |
8f996b89 | 840 | |
e73ffd42 BV |
841 | if (sdi->status != SR_ST_ACTIVE) |
842 | return SR_ERR_DEV_CLOSED; | |
843 | ||
0e1357e8 | 844 | devc = sdi->priv; |
99965709 | 845 | |
6868626b BV |
846 | switch (id) { |
847 | case SR_CONF_SAMPLERATE: | |
2c9c0df8 | 848 | ret = set_samplerate(sdi, g_variant_get_uint64(data)); |
6868626b BV |
849 | break; |
850 | case SR_CONF_LIMIT_MSEC: | |
2c9c0df8 | 851 | devc->limit_msec = g_variant_get_uint64(data); |
0e1357e8 | 852 | if (devc->limit_msec > 0) |
e46b8fb1 | 853 | ret = SR_OK; |
94ba4bd6 | 854 | else |
e46b8fb1 | 855 | ret = SR_ERR; |
6868626b BV |
856 | break; |
857 | case SR_CONF_LIMIT_SAMPLES: | |
858 | num_samples = g_variant_get_uint64(data); | |
859 | devc->limit_msec = num_samples * 1000 / devc->cur_samplerate; | |
860 | break; | |
861 | case SR_CONF_CAPTURE_RATIO: | |
2c9c0df8 | 862 | devc->capture_ratio = g_variant_get_uint64(data); |
0e1357e8 | 863 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) |
e46b8fb1 | 864 | ret = SR_ERR; |
94ba4bd6 | 865 | else |
e46b8fb1 | 866 | ret = SR_OK; |
6868626b BV |
867 | break; |
868 | default: | |
bd6fbf62 | 869 | ret = SR_ERR_NA; |
28a35d8a HE |
870 | } |
871 | ||
872 | return ret; | |
873 | } | |
874 | ||
8f996b89 | 875 | static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi, |
53b4680f | 876 | const struct sr_channel_group *cg) |
a1c743fc | 877 | { |
2c9c0df8 BV |
878 | GVariant *gvar; |
879 | GVariantBuilder gvb; | |
a1c743fc BV |
880 | |
881 | (void)sdi; | |
53b4680f | 882 | (void)cg; |
a1c743fc BV |
883 | |
884 | switch (key) { | |
9a6517d1 | 885 | case SR_CONF_DEVICE_OPTIONS: |
2c9c0df8 BV |
886 | *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32, |
887 | hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t)); | |
9a6517d1 | 888 | break; |
a1c743fc | 889 | case SR_CONF_SAMPLERATE: |
2c9c0df8 BV |
890 | g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}")); |
891 | gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates, | |
892 | ARRAY_SIZE(samplerates), sizeof(uint64_t)); | |
893 | g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar); | |
894 | *data = g_variant_builder_end(&gvb); | |
a1c743fc | 895 | break; |
c50277a6 | 896 | case SR_CONF_TRIGGER_TYPE: |
2c9c0df8 | 897 | *data = g_variant_new_string(TRIGGER_TYPE); |
c50277a6 | 898 | break; |
a1c743fc | 899 | default: |
bd6fbf62 | 900 | return SR_ERR_NA; |
a1c743fc BV |
901 | } |
902 | ||
903 | return SR_OK; | |
904 | } | |
905 | ||
36b1c8e6 | 906 | /* Software trigger to determine exact trigger position. */ |
5fc01191 | 907 | static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, |
36b1c8e6 HE |
908 | struct sigma_trigger *t) |
909 | { | |
910 | int i; | |
5fc01191 | 911 | uint16_t sample = 0; |
36b1c8e6 HE |
912 | |
913 | for (i = 0; i < 8; ++i) { | |
914 | if (i > 0) | |
5fc01191 MV |
915 | last_sample = sample; |
916 | sample = samples[2 * i] | (samples[2 * i + 1] << 8); | |
36b1c8e6 HE |
917 | |
918 | /* Simple triggers. */ | |
5fc01191 | 919 | if ((sample & t->simplemask) != t->simplevalue) |
36b1c8e6 HE |
920 | continue; |
921 | ||
922 | /* Rising edge. */ | |
5fc01191 MV |
923 | if (((last_sample & t->risingmask) != 0) || |
924 | ((sample & t->risingmask) != t->risingmask)) | |
36b1c8e6 HE |
925 | continue; |
926 | ||
927 | /* Falling edge. */ | |
bdfc7a89 | 928 | if ((last_sample & t->fallingmask) != t->fallingmask || |
5fc01191 | 929 | (sample & t->fallingmask) != 0) |
36b1c8e6 HE |
930 | continue; |
931 | ||
932 | break; | |
933 | } | |
934 | ||
935 | /* If we did not match, return original trigger pos. */ | |
936 | return i & 0x7; | |
937 | } | |
938 | ||
3513d965 MV |
939 | |
940 | /* | |
941 | * Return the timestamp of "DRAM cluster". | |
942 | */ | |
943 | static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster) | |
944 | { | |
945 | return (cluster->timestamp_hi << 8) | cluster->timestamp_lo; | |
946 | } | |
947 | ||
23239b5c MV |
948 | static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster, |
949 | unsigned int events_in_cluster, | |
1e23158b | 950 | unsigned int triggered, |
23239b5c MV |
951 | struct sr_dev_inst *sdi) |
952 | { | |
953 | struct dev_context *devc = sdi->priv; | |
954 | struct sigma_state *ss = &devc->state; | |
955 | struct sr_datafeed_packet packet; | |
956 | struct sr_datafeed_logic logic; | |
957 | uint16_t tsdiff, ts; | |
958 | uint8_t samples[2048]; | |
959 | unsigned int i; | |
960 | ||
23239b5c MV |
961 | ts = sigma_dram_cluster_ts(dram_cluster); |
962 | tsdiff = ts - ss->lastts; | |
963 | ss->lastts = ts; | |
964 | ||
965 | packet.type = SR_DF_LOGIC; | |
966 | packet.payload = &logic; | |
967 | logic.unitsize = 2; | |
968 | logic.data = samples; | |
969 | ||
970 | /* | |
971 | * First of all, send Sigrok a copy of the last sample from | |
972 | * previous cluster as many times as needed to make up for | |
973 | * the differential characteristics of data we get from the | |
974 | * Sigma. Sigrok needs one sample of data per period. | |
975 | * | |
976 | * One DRAM cluster contains a timestamp and seven samples, | |
977 | * the units of timestamp are "devc->period_ps" , the first | |
978 | * sample in the cluster happens at the time of the timestamp | |
979 | * and the remaining samples happen at timestamp +1...+6 . | |
980 | */ | |
981 | for (ts = 0; ts < tsdiff - (EVENTS_PER_CLUSTER - 1); ts++) { | |
982 | i = ts % 1024; | |
983 | samples[2 * i + 0] = ss->lastsample & 0xff; | |
984 | samples[2 * i + 1] = ss->lastsample >> 8; | |
985 | ||
986 | /* | |
987 | * If we have 1024 samples ready or we're at the | |
988 | * end of submitting the padding samples, submit | |
989 | * the packet to Sigrok. | |
990 | */ | |
991 | if ((i == 1023) || (ts == (tsdiff - EVENTS_PER_CLUSTER))) { | |
992 | logic.length = (i + 1) * logic.unitsize; | |
993 | sr_session_send(devc->cb_data, &packet); | |
994 | } | |
995 | } | |
996 | ||
997 | /* | |
998 | * Parse the samples in current cluster and prepare them | |
999 | * to be submitted to Sigrok. | |
1000 | */ | |
1001 | for (i = 0; i < events_in_cluster; i++) { | |
1002 | samples[2 * i + 1] = dram_cluster->samples[i].sample_lo; | |
1003 | samples[2 * i + 0] = dram_cluster->samples[i].sample_hi; | |
1004 | } | |
1005 | ||
1006 | /* Send data up to trigger point (if triggered). */ | |
1007 | int trigger_offset = 0; | |
1e23158b | 1008 | if (triggered) { |
23239b5c MV |
1009 | /* |
1010 | * Trigger is not always accurate to sample because of | |
1011 | * pipeline delay. However, it always triggers before | |
1012 | * the actual event. We therefore look at the next | |
1013 | * samples to pinpoint the exact position of the trigger. | |
1014 | */ | |
1015 | trigger_offset = get_trigger_offset(samples, | |
1016 | ss->lastsample, &devc->trigger); | |
1017 | ||
1018 | if (trigger_offset > 0) { | |
1019 | packet.type = SR_DF_LOGIC; | |
1020 | logic.length = trigger_offset * logic.unitsize; | |
1021 | sr_session_send(devc->cb_data, &packet); | |
1022 | events_in_cluster -= trigger_offset; | |
1023 | } | |
1024 | ||
1025 | /* Only send trigger if explicitly enabled. */ | |
1026 | if (devc->use_triggers) { | |
1027 | packet.type = SR_DF_TRIGGER; | |
1028 | sr_session_send(devc->cb_data, &packet); | |
1029 | } | |
1030 | } | |
1031 | ||
1032 | if (events_in_cluster > 0) { | |
1033 | packet.type = SR_DF_LOGIC; | |
1034 | logic.length = events_in_cluster * logic.unitsize; | |
1035 | logic.data = samples + (trigger_offset * logic.unitsize); | |
1036 | sr_session_send(devc->cb_data, &packet); | |
1037 | } | |
1038 | ||
1039 | ss->lastsample = | |
1040 | samples[2 * (events_in_cluster - 1) + 0] | | |
1041 | (samples[2 * (events_in_cluster - 1) + 1] << 8); | |
1042 | ||
1043 | } | |
1044 | ||
28a35d8a | 1045 | /* |
fefa1800 UH |
1046 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
1047 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
1048 | * |
1049 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
1050 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
1051 | * For 50 MHz and below, events contain one sample for each channel, | |
1052 | * spread 20 ns apart. | |
28a35d8a | 1053 | */ |
1e23158b MV |
1054 | static int decode_chunk_ts(struct sigma_dram_line *dram_line, |
1055 | uint16_t events_in_line, | |
1056 | uint32_t trigger_event, | |
1057 | void *cb_data) | |
28a35d8a | 1058 | { |
3628074d | 1059 | struct sigma_dram_cluster *dram_cluster; |
3cd3a20b | 1060 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 1061 | struct dev_context *devc = sdi->priv; |
5fc01191 MV |
1062 | unsigned int clusters_in_line = |
1063 | (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER; | |
1064 | unsigned int events_in_cluster; | |
23239b5c | 1065 | unsigned int i; |
1e23158b | 1066 | uint32_t trigger_cluster = ~0, triggered = 0; |
ee492173 | 1067 | |
4ae1f451 | 1068 | /* Check if trigger is in this chunk. */ |
1e23158b MV |
1069 | if (trigger_event < (64 * 7)) { |
1070 | if (devc->cur_samplerate <= SR_MHZ(50)) { | |
1071 | trigger_event -= MIN(EVENTS_PER_CLUSTER - 1, | |
1072 | trigger_event); | |
1073 | } | |
57bbf56b | 1074 | |
ee492173 | 1075 | /* Find in which cluster the trigger occured. */ |
1e23158b | 1076 | trigger_cluster = trigger_event / EVENTS_PER_CLUSTER; |
ee492173 | 1077 | } |
28a35d8a | 1078 | |
5fc01191 MV |
1079 | /* For each full DRAM cluster. */ |
1080 | for (i = 0; i < clusters_in_line; i++) { | |
3628074d | 1081 | dram_cluster = &dram_line->cluster[i]; |
5fc01191 | 1082 | |
5fc01191 | 1083 | /* The last cluster might not be full. */ |
23239b5c MV |
1084 | if ((i == clusters_in_line - 1) && |
1085 | (events_in_line % EVENTS_PER_CLUSTER)) { | |
5fc01191 | 1086 | events_in_cluster = events_in_line % EVENTS_PER_CLUSTER; |
23239b5c | 1087 | } else { |
5fc01191 | 1088 | events_in_cluster = EVENTS_PER_CLUSTER; |
abda62ce | 1089 | } |
ee492173 | 1090 | |
1e23158b MV |
1091 | triggered = (i == trigger_cluster); |
1092 | sigma_decode_dram_cluster(dram_cluster, events_in_cluster, | |
1093 | triggered, sdi); | |
28a35d8a HE |
1094 | } |
1095 | ||
e46b8fb1 | 1096 | return SR_OK; |
28a35d8a HE |
1097 | } |
1098 | ||
6057d9fa | 1099 | static int download_capture(struct sr_dev_inst *sdi) |
28a35d8a | 1100 | { |
6057d9fa | 1101 | struct dev_context *devc = sdi->priv; |
28a35d8a | 1102 | const int chunks_per_read = 32; |
fd830beb | 1103 | struct sigma_dram_line *dram_line; |
c6648b66 | 1104 | int bufsz; |
462fe786 | 1105 | uint32_t stoppos, triggerpos; |
6057d9fa MV |
1106 | struct sr_datafeed_packet packet; |
1107 | uint8_t modestatus; | |
1108 | ||
c6648b66 MV |
1109 | uint32_t i; |
1110 | uint32_t dl_lines_total, dl_lines_curr, dl_lines_done; | |
46641fac | 1111 | uint32_t dl_events_in_line = 64 * 7; |
1e23158b | 1112 | uint32_t trg_line = ~0, trg_event = ~0; |
c6648b66 | 1113 | |
fd830beb MV |
1114 | dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line)); |
1115 | if (!dram_line) | |
1116 | return FALSE; | |
1117 | ||
6868626b BV |
1118 | sr_info("Downloading sample data."); |
1119 | ||
6057d9fa MV |
1120 | /* Stop acquisition. */ |
1121 | sigma_set_register(WRITE_MODE, 0x11, devc); | |
1122 | ||
1123 | /* Set SDRAM Read Enable. */ | |
1124 | sigma_set_register(WRITE_MODE, 0x02, devc); | |
1125 | ||
1126 | /* Get the current position. */ | |
462fe786 | 1127 | sigma_read_pos(&stoppos, &triggerpos, devc); |
6057d9fa MV |
1128 | |
1129 | /* Check if trigger has fired. */ | |
1130 | modestatus = sigma_get_register(READ_MODE, devc); | |
1e23158b | 1131 | if (modestatus & 0x20) { |
c6648b66 | 1132 | trg_line = triggerpos >> 9; |
1e23158b MV |
1133 | trg_event = triggerpos & 0x1ff; |
1134 | } | |
6057d9fa | 1135 | |
c6648b66 MV |
1136 | /* |
1137 | * Determine how many 1024b "DRAM lines" do we need to read from the | |
1138 | * Sigma so we have a complete set of samples. Note that the last | |
1139 | * line can be only partial, containing less than 64 clusters. | |
1140 | */ | |
1141 | dl_lines_total = (stoppos >> 9) + 1; | |
6868626b | 1142 | |
c6648b66 | 1143 | dl_lines_done = 0; |
6868626b | 1144 | |
c6648b66 MV |
1145 | while (dl_lines_total > dl_lines_done) { |
1146 | /* We can download only up-to 32 DRAM lines in one go! */ | |
1147 | dl_lines_curr = MIN(chunks_per_read, dl_lines_total); | |
6868626b | 1148 | |
f41a4cae MV |
1149 | bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr, |
1150 | (uint8_t *)dram_line, devc); | |
c6648b66 MV |
1151 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1152 | (void)bufsz; | |
6868626b | 1153 | |
c6648b66 MV |
1154 | /* This is the first DRAM line, so find the initial timestamp. */ |
1155 | if (dl_lines_done == 0) { | |
3513d965 MV |
1156 | devc->state.lastts = |
1157 | sigma_dram_cluster_ts(&dram_line[0].cluster[0]); | |
c6648b66 | 1158 | devc->state.lastsample = 0; |
6868626b BV |
1159 | } |
1160 | ||
c6648b66 | 1161 | for (i = 0; i < dl_lines_curr; i++) { |
1e23158b | 1162 | uint32_t trigger_event = ~0; |
c6648b66 MV |
1163 | /* The last "DRAM line" can be only partially full. */ |
1164 | if (dl_lines_done + i == dl_lines_total - 1) | |
46641fac | 1165 | dl_events_in_line = stoppos & 0x1ff; |
c6648b66 | 1166 | |
e69ad48e | 1167 | /* Test if the trigger happened on this line. */ |
c6648b66 | 1168 | if (dl_lines_done + i == trg_line) |
1e23158b | 1169 | trigger_event = trg_event; |
e69ad48e | 1170 | |
1e23158b MV |
1171 | decode_chunk_ts(dram_line + i, dl_events_in_line, |
1172 | trigger_event, sdi); | |
c6648b66 | 1173 | } |
6868626b | 1174 | |
c6648b66 | 1175 | dl_lines_done += dl_lines_curr; |
6868626b BV |
1176 | } |
1177 | ||
6057d9fa MV |
1178 | /* All done. */ |
1179 | packet.type = SR_DF_END; | |
1180 | sr_session_send(sdi, &packet); | |
1181 | ||
1182 | dev_acquisition_stop(sdi, sdi); | |
1183 | ||
fd830beb MV |
1184 | g_free(dram_line); |
1185 | ||
6057d9fa | 1186 | return TRUE; |
6868626b BV |
1187 | } |
1188 | ||
d4051930 MV |
1189 | /* |
1190 | * Handle the Sigma when in CAPTURE mode. This function checks: | |
1191 | * - Sampling time ended | |
1192 | * - DRAM capacity overflow | |
1193 | * This function triggers download of the samples from Sigma | |
1194 | * in case either of the above conditions is true. | |
1195 | */ | |
1196 | static int sigma_capture_mode(struct sr_dev_inst *sdi) | |
6868626b | 1197 | { |
d4051930 MV |
1198 | struct dev_context *devc = sdi->priv; |
1199 | ||
94ba4bd6 | 1200 | uint64_t running_msec; |
28a35d8a | 1201 | struct timeval tv; |
28a35d8a | 1202 | |
00c86508 | 1203 | uint32_t stoppos, triggerpos; |
28a35d8a | 1204 | |
00c86508 | 1205 | /* Check if the selected sampling duration passed. */ |
d4051930 MV |
1206 | gettimeofday(&tv, 0); |
1207 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + | |
00c86508 MV |
1208 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; |
1209 | if (running_msec >= devc->limit_msec) | |
6057d9fa | 1210 | return download_capture(sdi); |
00c86508 MV |
1211 | |
1212 | /* Get the position in DRAM to which the FPGA is writing now. */ | |
1213 | sigma_read_pos(&stoppos, &triggerpos, devc); | |
1214 | /* Test if DRAM is full and if so, download the data. */ | |
1215 | if ((stoppos >> 9) == 32767) | |
6057d9fa | 1216 | return download_capture(sdi); |
28a35d8a | 1217 | |
d4051930 MV |
1218 | return TRUE; |
1219 | } | |
28a35d8a | 1220 | |
d4051930 MV |
1221 | static int receive_data(int fd, int revents, void *cb_data) |
1222 | { | |
1223 | struct sr_dev_inst *sdi; | |
1224 | struct dev_context *devc; | |
88c51afe | 1225 | |
d4051930 MV |
1226 | (void)fd; |
1227 | (void)revents; | |
88c51afe | 1228 | |
d4051930 MV |
1229 | sdi = cb_data; |
1230 | devc = sdi->priv; | |
1231 | ||
1232 | if (devc->state.state == SIGMA_IDLE) | |
1233 | return TRUE; | |
1234 | ||
1235 | if (devc->state.state == SIGMA_CAPTURE) | |
1236 | return sigma_capture_mode(sdi); | |
28a35d8a | 1237 | |
28a35d8a HE |
1238 | return TRUE; |
1239 | } | |
1240 | ||
c53d793f HE |
1241 | /* Build a LUT entry used by the trigger functions. */ |
1242 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1243 | { |
1244 | int i, j, k, bit; | |
1245 | ||
ba7dd8bb | 1246 | /* For each quad channel. */ |
ee492173 | 1247 | for (i = 0; i < 4; ++i) { |
c53d793f | 1248 | entry[i] = 0xffff; |
ee492173 | 1249 | |
f758d074 | 1250 | /* For each bit in LUT. */ |
ee492173 HE |
1251 | for (j = 0; j < 16; ++j) |
1252 | ||
ba7dd8bb | 1253 | /* For each channel in quad. */ |
ee492173 HE |
1254 | for (k = 0; k < 4; ++k) { |
1255 | bit = 1 << (i * 4 + k); | |
1256 | ||
c53d793f HE |
1257 | /* Set bit in entry */ |
1258 | if ((mask & bit) && | |
1259 | ((!(value & bit)) != | |
4ae1f451 | 1260 | (!(j & (1 << k))))) |
c53d793f | 1261 | entry[i] &= ~(1 << j); |
ee492173 HE |
1262 | } |
1263 | } | |
c53d793f | 1264 | } |
ee492173 | 1265 | |
c53d793f HE |
1266 | /* Add a logical function to LUT mask. */ |
1267 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1268 | int index, int neg, uint16_t *mask) | |
1269 | { | |
1270 | int i, j; | |
1271 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1272 | ||
1273 | memset(x, 0, 4 * sizeof(int)); | |
1274 | ||
1275 | /* Trigger detect condition. */ | |
1276 | switch (oper) { | |
1277 | case OP_LEVEL: | |
1278 | x[0][1] = 1; | |
1279 | x[1][1] = 1; | |
1280 | break; | |
1281 | case OP_NOT: | |
1282 | x[0][0] = 1; | |
1283 | x[1][0] = 1; | |
1284 | break; | |
1285 | case OP_RISE: | |
1286 | x[0][1] = 1; | |
1287 | break; | |
1288 | case OP_FALL: | |
1289 | x[1][0] = 1; | |
1290 | break; | |
1291 | case OP_RISEFALL: | |
1292 | x[0][1] = 1; | |
1293 | x[1][0] = 1; | |
1294 | break; | |
1295 | case OP_NOTRISE: | |
1296 | x[1][1] = 1; | |
1297 | x[0][0] = 1; | |
1298 | x[1][0] = 1; | |
1299 | break; | |
1300 | case OP_NOTFALL: | |
1301 | x[1][1] = 1; | |
1302 | x[0][0] = 1; | |
1303 | x[0][1] = 1; | |
1304 | break; | |
1305 | case OP_NOTRISEFALL: | |
1306 | x[1][1] = 1; | |
1307 | x[0][0] = 1; | |
1308 | break; | |
1309 | } | |
1310 | ||
1311 | /* Transpose if neg is set. */ | |
1312 | if (neg) { | |
ea9cfed7 | 1313 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1314 | for (j = 0; j < 2; ++j) { |
1315 | tmp = x[i][j]; | |
1316 | x[i][j] = x[1-i][1-j]; | |
1317 | x[1-i][1-j] = tmp; | |
1318 | } | |
ea9cfed7 | 1319 | } |
c53d793f HE |
1320 | } |
1321 | ||
1322 | /* Update mask with function. */ | |
1323 | for (i = 0; i < 16; ++i) { | |
1324 | a = (i >> (2 * index + 0)) & 1; | |
1325 | b = (i >> (2 * index + 1)) & 1; | |
1326 | ||
1327 | aset = (*mask >> i) & 1; | |
1328 | bset = x[b][a]; | |
1329 | ||
1330 | if (func == FUNC_AND || func == FUNC_NAND) | |
1331 | rset = aset & bset; | |
1332 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1333 | rset = aset | bset; | |
1334 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1335 | rset = aset ^ bset; | |
1336 | ||
1337 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1338 | rset = !rset; | |
1339 | ||
1340 | *mask &= ~(1 << i); | |
1341 | ||
1342 | if (rset) | |
1343 | *mask |= 1 << i; | |
1344 | } | |
1345 | } | |
1346 | ||
1347 | /* | |
1348 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1349 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1350 | * set at any time, but a full mask and value can be set (0/1). | |
1351 | */ | |
0e1357e8 | 1352 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1353 | { |
1354 | int i,j; | |
4ae1f451 | 1355 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1356 | |
1357 | memset(lut, 0, sizeof(struct triggerlut)); | |
1358 | ||
1359 | /* Contant for simple triggers. */ | |
1360 | lut->m4 = 0xa000; | |
1361 | ||
1362 | /* Value/mask trigger support. */ | |
0e1357e8 | 1363 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1364 | lut->m2d); |
c53d793f HE |
1365 | |
1366 | /* Rise/fall trigger support. */ | |
1367 | for (i = 0, j = 0; i < 16; ++i) { | |
0e1357e8 BV |
1368 | if (devc->trigger.risingmask & (1 << i) || |
1369 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1370 | masks[j++] = 1 << i; |
1371 | } | |
1372 | ||
1373 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1374 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1375 | ||
1376 | /* Add glue logic */ | |
1377 | if (masks[0] || masks[1]) { | |
1378 | /* Transition trigger. */ | |
0e1357e8 | 1379 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1380 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1381 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1382 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1383 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1384 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1385 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1386 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1387 | } else { | |
1388 | /* Only value/mask trigger. */ | |
1389 | lut->m3 = 0xffff; | |
1390 | } | |
ee492173 | 1391 | |
c53d793f | 1392 | /* Triggertype: event. */ |
ee492173 HE |
1393 | lut->params.selres = 3; |
1394 | ||
e46b8fb1 | 1395 | return SR_OK; |
ee492173 HE |
1396 | } |
1397 | ||
6078d2c9 | 1398 | static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1399 | { |
0e1357e8 | 1400 | struct dev_context *devc; |
9ddb2a12 | 1401 | struct clockselect_50 clockselect; |
82957b65 | 1402 | int frac, triggerpin, ret; |
f4abaa9f | 1403 | uint8_t triggerselect = 0; |
57bbf56b | 1404 | struct triggerinout triggerinout_conf; |
ee492173 | 1405 | struct triggerlut lut; |
28a35d8a | 1406 | |
e73ffd42 BV |
1407 | if (sdi->status != SR_ST_ACTIVE) |
1408 | return SR_ERR_DEV_CLOSED; | |
1409 | ||
0e1357e8 | 1410 | devc = sdi->priv; |
28a35d8a | 1411 | |
ba7dd8bb UH |
1412 | if (configure_channels(sdi) != SR_OK) { |
1413 | sr_err("Failed to configure channels."); | |
014359e3 BV |
1414 | return SR_ERR; |
1415 | } | |
1416 | ||
ea9cfed7 | 1417 | /* If the samplerate has not been set, default to 200 kHz. */ |
0e1357e8 | 1418 | if (devc->cur_firmware == -1) { |
82957b65 UH |
1419 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1420 | return ret; | |
1421 | } | |
e8397563 | 1422 | |
eec5275e | 1423 | /* Enter trigger programming mode. */ |
0e1357e8 | 1424 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); |
28a35d8a | 1425 | |
eec5275e | 1426 | /* 100 and 200 MHz mode. */ |
0e1357e8 BV |
1427 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
1428 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
57bbf56b | 1429 | |
a42aec7f HE |
1430 | /* Find which pin to trigger on from mask. */ |
1431 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
0e1357e8 | 1432 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & |
a42aec7f HE |
1433 | (1 << triggerpin)) |
1434 | break; | |
1435 | ||
1436 | /* Set trigger pin and light LED on trigger. */ | |
1437 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1438 | ||
1439 | /* Default rising edge. */ | |
0e1357e8 | 1440 | if (devc->trigger.fallingmask) |
a42aec7f | 1441 | triggerselect |= 1 << 3; |
57bbf56b | 1442 | |
eec5275e | 1443 | /* All other modes. */ |
0e1357e8 BV |
1444 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { |
1445 | build_basic_trigger(&lut, devc); | |
ee492173 | 1446 | |
0e1357e8 | 1447 | sigma_write_trigger_lut(&lut, devc); |
57bbf56b HE |
1448 | |
1449 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1450 | } | |
1451 | ||
eec5275e | 1452 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1453 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1454 | triggerinout_conf.trgout_bytrigger = 1; | |
1455 | triggerinout_conf.trgout_enable = 1; | |
1456 | ||
28a35d8a | 1457 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1458 | (uint8_t *) &triggerinout_conf, |
0e1357e8 | 1459 | sizeof(struct triggerinout), devc); |
28a35d8a | 1460 | |
eec5275e | 1461 | /* Go back to normal mode. */ |
0e1357e8 | 1462 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); |
28a35d8a | 1463 | |
edca2c5c | 1464 | /* Set clock select register. */ |
0e1357e8 | 1465 | if (devc->cur_samplerate == SR_MHZ(200)) |
ba7dd8bb | 1466 | /* Enable 4 channels. */ |
0e1357e8 BV |
1467 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); |
1468 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
ba7dd8bb | 1469 | /* Enable 8 channels. */ |
0e1357e8 | 1470 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); |
edca2c5c HE |
1471 | else { |
1472 | /* | |
9ddb2a12 | 1473 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1474 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1475 | */ |
0e1357e8 | 1476 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; |
edca2c5c | 1477 | |
9ddb2a12 UH |
1478 | clockselect.async = 0; |
1479 | clockselect.fraction = frac; | |
ba7dd8bb | 1480 | clockselect.disabled_channels = 0; |
edca2c5c HE |
1481 | |
1482 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1483 | (uint8_t *) &clockselect, |
0e1357e8 | 1484 | sizeof(clockselect), devc); |
edca2c5c HE |
1485 | } |
1486 | ||
fefa1800 | 1487 | /* Setup maximum post trigger time. */ |
99965709 | 1488 | sigma_set_register(WRITE_POST_TRIGGER, |
0e1357e8 | 1489 | (devc->capture_ratio * 255) / 100, devc); |
28a35d8a | 1490 | |
eec5275e | 1491 | /* Start acqusition. */ |
0e1357e8 BV |
1492 | gettimeofday(&devc->start_tv, 0); |
1493 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
99965709 | 1494 | |
3e9b7f9c | 1495 | devc->cb_data = cb_data; |
28a35d8a | 1496 | |
3c36c403 | 1497 | /* Send header packet to the session bus. */ |
29a27196 | 1498 | std_session_send_df_header(cb_data, LOG_PREFIX); |
f366e86c | 1499 | |
f366e86c | 1500 | /* Add capture source. */ |
3ffb6964 | 1501 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); |
f366e86c | 1502 | |
0e1357e8 | 1503 | devc->state.state = SIGMA_CAPTURE; |
6aac7737 | 1504 | |
e46b8fb1 | 1505 | return SR_OK; |
28a35d8a HE |
1506 | } |
1507 | ||
6078d2c9 | 1508 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1509 | { |
0e1357e8 | 1510 | struct dev_context *devc; |
6aac7737 | 1511 | |
3cd3a20b | 1512 | (void)cb_data; |
28a35d8a | 1513 | |
6868626b BV |
1514 | devc = sdi->priv; |
1515 | devc->state.state = SIGMA_IDLE; | |
6aac7737 | 1516 | |
6868626b | 1517 | sr_source_remove(0); |
3010f21c UH |
1518 | |
1519 | return SR_OK; | |
28a35d8a HE |
1520 | } |
1521 | ||
c09f0b57 | 1522 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 | 1523 | .name = "asix-sigma", |
6352d030 | 1524 | .longname = "ASIX SIGMA/SIGMA2", |
e519ba86 | 1525 | .api_version = 1, |
6078d2c9 UH |
1526 | .init = init, |
1527 | .cleanup = cleanup, | |
1528 | .scan = scan, | |
1529 | .dev_list = dev_list, | |
3b412e3a | 1530 | .dev_clear = dev_clear, |
035a1078 BV |
1531 | .config_get = config_get, |
1532 | .config_set = config_set, | |
a1c743fc | 1533 | .config_list = config_list, |
6078d2c9 UH |
1534 | .dev_open = dev_open, |
1535 | .dev_close = dev_close, | |
1536 | .dev_acquisition_start = dev_acquisition_start, | |
1537 | .dev_acquisition_stop = dev_acquisition_stop, | |
0e1357e8 | 1538 | .priv = NULL, |
28a35d8a | 1539 | }; |