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66a8517e | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
66a8517e UH |
3 | ## |
4 | ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
66a8517e UH |
21 | import sigrokdecode as srd |
22 | ||
23 | # JTAG debug port data registers (in IR[3:0]) and their sizes (in bits) | |
457acc28 UH |
24 | # Note: The ARM DAP-DP is not IEEE 1149.1 (JTAG) compliant (as per ARM docs), |
25 | # as it does not implement the EXTEST, SAMPLE, and PRELOAD instructions. | |
26 | # Instead, BYPASS is decoded for any of these instructions. | |
66a8517e UH |
27 | ir = { |
28 | '1111': ['BYPASS', 1], # Bypass register | |
29 | '1110': ['IDCODE', 32], # ID code register | |
30 | '1010': ['DPACC', 35], # Debug port access register | |
31 | '1011': ['APACC', 35], # Access port access register | |
e9656a0c | 32 | '1000': ['ABORT', 35], # Abort register # TODO: 32 bits? Datasheet typo? |
66a8517e UH |
33 | } |
34 | ||
35 | # ARM Cortex-M3 r1p1-01rel0 ID code | |
36 | cm3_idcode = 0x3ba00477 | |
37 | ||
38 | # JTAG ID code in the STM32F10xxx BSC (boundary scan) TAP | |
39 | jtag_idcode = { | |
40 | 0x06412041: 'Low-density device, rev. A', | |
41 | 0x06410041: 'Medium-density device, rev. A', | |
42 | 0x16410041: 'Medium-density device, rev. B/Z/Y', | |
43 | 0x06414041: 'High-density device, rev. A/Z/Y', | |
44 | 0x06430041: 'XL-density device, rev. A', | |
45 | 0x06418041: 'Connectivity-line device, rev. A/Z', | |
46 | } | |
47 | ||
d274e1bf | 48 | # ACK[2:0] in the DPACC/APACC registers (unlisted values are reserved) |
66a8517e | 49 | ack_val = { |
66a8517e UH |
50 | '001': 'WAIT', |
51 | '010': 'OK/FAULT', | |
66a8517e UH |
52 | } |
53 | ||
54 | # 32bit debug port registers (addressed via A[3:2]) | |
d274e1bf | 55 | dp_reg = { |
66a8517e UH |
56 | '00': 'Reserved', # Must be kept at reset value |
57 | '01': 'DP CTRL/STAT', | |
58 | '10': 'DP SELECT', | |
59 | '11': 'DP RDBUFF', | |
60 | } | |
61 | ||
d274e1bf UH |
62 | # APB-AP registers (each of them 32 bits wide) |
63 | apb_ap_reg = { | |
64 | 0x00: ['CSW', 'Control/status word'], | |
65 | 0x04: ['TAR', 'Transfer address'], | |
66 | # 0x08: Reserved SBZ | |
67 | 0x0c: ['DRW', 'Data read/write'], | |
68 | 0x10: ['BD0', 'Banked data 0'], | |
69 | 0x14: ['BD1', 'Banked data 1'], | |
70 | 0x18: ['BD2', 'Banked data 2'], | |
71 | 0x1c: ['BD3', 'Banked data 3'], | |
72 | # 0x20-0xf4: Reserved SBZ | |
73 | 0x800000000: ['ROM', 'Debug ROM address'], | |
74 | 0xfc: ['IDR', 'Identification register'], | |
75 | } | |
76 | ||
e9656a0c | 77 | # TODO: All start/end sample values in self.put() calls are bogus. |
d274e1bf | 78 | # TODO: Split off generic ARM/Cortex-M3 parts into another protocol decoder? |
e9656a0c | 79 | |
457acc28 UH |
80 | # Bits[31:28]: Version (here: 0x3) |
81 | # JTAG-DP: 0x3, SW-DP: 0x2 | |
82 | # Bits[27:12]: Part number (here: 0xba00) | |
83 | # JTAG-DP: 0xba00, SW-DP: 0xba10 | |
84 | # Bits[11:1]: JEDEC (JEP-106) manufacturer ID (here: 0x23b) | |
85 | # Bits[11:8]: Continuation code ('ARM Limited': 0x04) | |
86 | # Bits[7:1]: Identity code ('ARM Limited': 0x3b) | |
87 | # Bits[0:0]: Reserved (here: 0x1) | |
88 | def decode_device_id_code(bits): | |
89 | id_hex = '0x%x' % int('0b' + bits, 2) | |
90 | ver = '0x%x' % int('0b' + bits[-32:-28], 2) | |
91 | part = '0x%x' % int('0b' + bits[-28:-12], 2) | |
92 | manuf = '0x%x' % int('0b' + bits[-12:-1], 2) | |
93 | res = '0x%x' % int('0b' + bits[-1], 2) | |
94 | return (id_hex, ver, part, manuf, res) | |
95 | ||
d274e1bf UH |
96 | # DPACC is used to access debug port registers (CTRL/STAT, SELECT, RDBUFF). |
97 | # APACC is used to access all Access Port (AHB-AP) registers. | |
98 | ||
99 | # APACC/DPACC, when transferring data IN: | |
100 | # Bits[34:3] = DATA[31:0]: 32bit data to transfer (write request) | |
101 | # Bits[2:1] = A[3:2]: 2-bit address (debug/access port register) | |
102 | # Bits[0:0] = RnW: Read request (1) or write request (0) | |
103 | def data_in(instruction, bits): | |
c840e704 UH |
104 | data, a, rnw = bits[:-3], bits[-3:-1], bits[-1] |
105 | data_hex = '0x%x' % int('0b' + data, 2) | |
106 | r = 'Read request' if (rnw == '1') else 'Write request' | |
d274e1bf UH |
107 | # reg = dp_reg[a] if (instruction == 'DPACC') else apb_ap_reg[a] |
108 | reg = dp_reg[a] if (instruction == 'DPACC') else a # TODO | |
109 | return 'New transaction: DATA: %s, A: %s, RnW: %s' % (data_hex, reg, r) | |
110 | ||
111 | # APACC/DPACC, when transferring data OUT: | |
112 | # Bits[34:3] = DATA[31:0]: 32bit data which is read (read request) | |
113 | # Bits[2:0] = ACK[2:0]: 3-bit acknowledge | |
114 | def data_out(bits): | |
c840e704 UH |
115 | data, ack = bits[:-3], bits[-3:] |
116 | data_hex = '0x%x' % int('0b' + data, 2) | |
d274e1bf UH |
117 | ack_meaning = ack_val.get(ack, 'Reserved') |
118 | return 'Previous transaction result: DATA: %s, ACK: %s' \ | |
119 | % (data_hex, ack_meaning) | |
c840e704 | 120 | |
66a8517e | 121 | class Decoder(srd.Decoder): |
12851357 | 122 | api_version = 2 |
66a8517e UH |
123 | id = 'jtag_stm32' |
124 | name = 'JTAG / STM32' | |
125 | longname = 'Joint Test Action Group / ST STM32' | |
126 | desc = 'ST STM32-specific JTAG protocol.' | |
127 | license = 'gplv2+' | |
128 | inputs = ['jtag'] | |
129 | outputs = ['jtag_stm32'] | |
da9bcbd9 BV |
130 | annotations = ( |
131 | ('text', 'Human-readable text'), | |
132 | ) | |
66a8517e UH |
133 | |
134 | def __init__(self, **kwargs): | |
135 | self.state = 'IDLE' | |
e9656a0c | 136 | # self.state = 'BYPASS' |
66a8517e | 137 | |
8915b346 | 138 | def start(self): |
be465111 | 139 | self.out_ann = self.register(srd.OUTPUT_ANN) |
66a8517e | 140 | |
d274e1bf | 141 | def handle_reg_bypass(self, cmd, bits): |
66a8517e | 142 | # TODO |
e9656a0c | 143 | self.put(self.ss, self.es, self.out_ann, [0, ['BYPASS: ' + bits]]) |
66a8517e | 144 | |
d274e1bf | 145 | def handle_reg_idcode(self, cmd, bits): |
66a8517e | 146 | # TODO |
c840e704 UH |
147 | # IDCODE is a read-only register which is always accessible. |
148 | # IR == IDCODE: The device ID code is shifted out via DR next. | |
e9656a0c | 149 | self.put(self.ss, self.es, self.out_ann, |
457acc28 UH |
150 | [0, ['IDCODE: %s (ver=%s, part=%s, manuf=%s, res=%s)' % \ |
151 | decode_device_id_code(bits)]]) | |
66a8517e | 152 | |
d274e1bf UH |
153 | def handle_reg_dpacc(self, cmd, bits): |
154 | # self.put(self.ss, self.es, self.out_ann, | |
155 | # [0, ['DPACC/%s: %s' % (cmd, bits)]]) | |
156 | s = data_in('DPACC', bits) if (cmd == 'DR TDI') else data_out(bits) | |
157 | self.put(self.ss, self.es, self.out_ann, [0, [s]]) | |
158 | ||
159 | def handle_reg_apacc(self, cmd, bits): | |
160 | # self.put(self.ss, self.es, self.out_ann, | |
161 | # [0, ['APACC/%s: %s' % (cmd, bits)]]) | |
162 | s = data_in('APACC', bits) if (cmd == 'DR TDI') else data_out(bits) | |
163 | self.put(self.ss, self.es, self.out_ann, [0, [s]]) | |
164 | ||
165 | def handle_reg_abort(self, cmd, bits): | |
66a8517e UH |
166 | # Bits[31:1]: reserved. Bit[0]: DAPABORT. |
167 | a = '' if (bits[0] == '1') else 'No ' | |
168 | s = 'DAPABORT = %s: %sDAP abort generated' % (bits[0], a) | |
169 | self.put(self.ss, self.es, self.out_ann, [0, [s]]) | |
170 | ||
e9656a0c | 171 | # Warn if DAPABORT[31:1] contains non-zero bits. |
66a8517e | 172 | if (bits[:-1] != ('0' * 31)): |
e9656a0c UH |
173 | self.put(self.ss, self.es, self.out_ann, |
174 | [0, ['WARNING: DAPABORT[31:1] reserved!']]) | |
175 | ||
d274e1bf | 176 | def handle_reg_unknown(self, cmd, bits): |
e9656a0c UH |
177 | self.put(self.ss, self.es, self.out_ann, |
178 | [0, ['Unknown instruction: ' % bits]]) # TODO | |
66a8517e UH |
179 | |
180 | def decode(self, ss, es, data): | |
181 | # Assumption: The right-most char in the 'val' bitstring is the LSB. | |
182 | cmd, val = data | |
183 | ||
184 | self.ss, self.es = ss, es | |
185 | ||
e9656a0c | 186 | # self.put(self.ss, self.es, self.out_ann, [0, [cmd + ' / ' + val]]) |
66a8517e UH |
187 | |
188 | # State machine | |
e9656a0c UH |
189 | if self.state == 'IDLE': |
190 | # Wait until a new instruction is shifted into the IR register. | |
191 | if cmd != 'IR TDI': | |
192 | return | |
193 | # Switch to the state named after the instruction, or 'UNKNOWN'. | |
d274e1bf UH |
194 | # Ignore bits other than IR[3:0]. While the IR register is only |
195 | # 4 bits in size, some programs (e.g. OpenOCD) might fill in a | |
196 | # few more (dummy) bits. OpenOCD makes IR at least 8 bits long. | |
e9656a0c UH |
197 | self.state = ir.get(val[-4:], ['UNKNOWN', 0])[0] |
198 | self.put(self.ss, self.es, self.out_ann, [0, ['IR: ' + self.state]]) | |
d274e1bf UH |
199 | elif self.state == 'BYPASS': |
200 | # Here we're interested in incoming bits (TDI). | |
e9656a0c UH |
201 | if cmd != 'DR TDI': |
202 | return | |
203 | handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower()) | |
d274e1bf | 204 | handle_reg(cmd, val) |
e9656a0c | 205 | self.state = 'IDLE' |
d274e1bf UH |
206 | elif self.state in ('IDCODE', 'ABORT', 'UNKNOWN'): |
207 | # Here we're interested in outgoing bits (TDO). | |
457acc28 | 208 | if cmd != 'DR TDO': |
e9656a0c UH |
209 | return |
210 | handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower()) | |
d274e1bf | 211 | handle_reg(cmd, val) |
e9656a0c | 212 | self.state = 'IDLE' |
d274e1bf UH |
213 | elif self.state in ('DPACC', 'APACC'): |
214 | # Here we're interested in incoming and outgoing bits (TDI/TDO). | |
215 | if cmd not in ('DR TDI', 'DR TDO'): | |
216 | return | |
217 | handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower()) | |
218 | handle_reg(cmd, val) | |
219 | if cmd == 'DR TDO': # TODO: Assumes 'DR TDI' comes before 'DR TDO' | |
220 | self.state = 'IDLE' | |
e9656a0c UH |
221 | else: |
222 | raise Exception('Invalid state: %s' % self.state) | |
66a8517e | 223 |