[libsigrokdecode.git] / decoders / jtag_stm32 / jtag_stm32.py

##
## This file is part of the sigrok project.
##
## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

# ST STM32 JTAG protocol decoder

import sigrokdecode as srd

# JTAG debug port data registers (in IR[3:0]) and their sizes (in bits)
# Note: The ARM DAP-DP is not IEEE 1149.1 (JTAG) compliant (as per ARM docs),
#       as it does not implement the EXTEST, SAMPLE, and PRELOAD instructions.
#       Instead, BYPASS is decoded for any of these instructions.
ir = {
    '1111': ['BYPASS', 1],  # Bypass register
    '1110': ['IDCODE', 32], # ID code register
    '1010': ['DPACC', 35],  # Debug port access register
    '1011': ['APACC', 35],  # Access port access register
    '1000': ['ABORT', 35],  # Abort register # TODO: 32 bits? Datasheet typo?
}

# ARM Cortex-M3 r1p1-01rel0 ID code
cm3_idcode = 0x3ba00477

# JTAG ID code in the STM32F10xxx BSC (boundary scan) TAP
jtag_idcode = {
    0x06412041: 'Low-density device, rev. A',
    0x06410041: 'Medium-density device, rev. A',
    0x16410041: 'Medium-density device, rev. B/Z/Y',
    0x06414041: 'High-density device, rev. A/Z/Y',
    0x06430041: 'XL-density device, rev. A',
    0x06418041: 'Connectivity-line device, rev. A/Z',
}

# ACK[2:0] in the DPACC/APACC registers
ack_val = {
    '000': 'Reserved',
    '001': 'WAIT',
    '010': 'OK/FAULT',
    '011': 'Reserved',
    '100': 'Reserved',
    '101': 'Reserved',
    '110': 'Reserved',
    '111': 'Reserved',
}

# 32bit debug port registers (addressed via A[3:2])
reg = {
    '00': 'Reserved', # Must be kept at reset value
    '01': 'DP CTRL/STAT',
    '10': 'DP SELECT',
    '11': 'DP RDBUFF',
}

# TODO: All start/end sample values in self.put() calls are bogus.

# Bits[31:28]: Version (here: 0x3)
#              JTAG-DP: 0x3, SW-DP: 0x2
# Bits[27:12]: Part number (here: 0xba00)
#              JTAG-DP: 0xba00, SW-DP: 0xba10
# Bits[11:1]:  JEDEC (JEP-106) manufacturer ID (here: 0x23b)
#              Bits[11:8]: Continuation code ('ARM Limited': 0x04)
#              Bits[7:1]: Identity code ('ARM Limited': 0x3b)
# Bits[0:0]:   Reserved (here: 0x1)
def decode_device_id_code(bits):
    id_hex = '0x%x' % int('0b' + bits, 2)
    ver =    '0x%x' % int('0b' + bits[-32:-28], 2)
    part =   '0x%x' % int('0b' + bits[-28:-12], 2)
    manuf =  '0x%x' % int('0b' + bits[-12:-1], 2)
    res =    '0x%x' % int('0b' + bits[-1], 2)
    return (id_hex, ver, part, manuf, res)

class Decoder(srd.Decoder):
    api_version = 1
    id = 'jtag_stm32'
    name = 'JTAG / STM32'
    longname = 'Joint Test Action Group / ST STM32'
    desc = 'ST STM32-specific JTAG protocol.'
    license = 'gplv2+'
    inputs = ['jtag']
    outputs = ['jtag_stm32']
    probes = []
    optional_probes = []
    options = {}
    annotations = [
        ['Text', 'Human-readable text'],
    ]

    def __init__(self, **kwargs):
        self.state = 'IDLE'
        # self.state = 'BYPASS'

    def start(self, metadata):
        # self.out_proto = self.add(srd.OUTPUT_PROTO, 'jtag_stm32')
        self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag_stm32')

    def report(self):
        pass

    def handle_reg_bypass(self, bits):
        # TODO
        self.put(self.ss, self.es, self.out_ann, [0, ['BYPASS: ' + bits]])

    def handle_reg_idcode(self, bits):
        # TODO
        self.put(self.ss, self.es, self.out_ann,
                 [0, ['IDCODE: %s (ver=%s, part=%s, manuf=%s, res=%s)' % \
                 decode_device_id_code(bits)]])

    # When transferring data IN:
    #   Bits[34:3] = DATA[31:0]: 32bit data to transfer (write request)
    #   Bits[2:1] = A[3:2]: 2-bit address of a debug port register
    #   Bits[0:0] = RnW: Read request (1) or write request (0)
    # When transferring data OUT:
    #   Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
    #   Bits[2:0] = ACK[2:0]: 3-bit acknowledge
    def handle_reg_dpacc(self, bits):
        self.put(self.ss, self.es, self.out_ann, [0, ['DPACC: ' + bits]])

        # TODO: When to use Data IN / Data OUT?

        # Data IN
        data, a, rnw = bits[:-3], bits[-3:-1], bits[-1]
        data_hex = '0x%x' % int('0b' + data, 2)
        r = 'Read request' if (rnw == '1') else 'Write request'
        s = 'DATA: %s, A: %s, RnW: %s' % (data_hex, reg[a], r)
        self.put(self.ss, self.es, self.out_ann, [0, [s]])

        # Data OUT
        data, ack = bits[:-3], bits[-3:]
        data_hex = '0x%x' % int('0b' + data, 2)
        ack_meaning = ack_val[ack]
        s = 'DATA: %s, ACK: %s' % (data_hex, ack_meaning)
        self.put(self.ss, self.es, self.out_ann, [0, [s]])

    # When transferring data IN:
    #   Bits[34:3] = DATA[31:0]: 32bit data to shift in (write request)
    #   Bits[2:1] = A[3:2]: 2-bit address (sub-address AP register)
    #   Bits[0:0] = RnW: Read request (1) or write request (0)
    # When transferring data OUT:
    #   Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
    #   Bits[2:0] = ACK[2:0]: 3-bit acknowledge
    def handle_reg_apacc(self, bits):
        self.put(self.ss, self.es, self.out_ann, [0, ['APACC: ' + bits]])

        # TODO: When to use Data IN / Data OUT?

        # Data IN
        data, a, rnw = bits[:-3], bits[-3:-1], bits[-1]
        data_hex = '0x%x' % int('0b' + data, 2)
        r = 'Read request' if (rnw == '1') else 'Write request'
        s = 'DATA: %s, A: %s, RnW: %s' % (data_hex, reg[a], r)
        self.put(self.ss, self.es, self.out_ann, [0, [s]])

        # Data OUT
        data, ack = bits[:-3], bits[-3:]
        data_hex = '0x%x' % int('0b' + data, 2)
        ack_meaning = ack_val[ack]
        s = 'DATA: %s, ACK: %s' % (data_hex, ack_meaning)
        self.put(self.ss, self.es, self.out_ann, [0, [s]])

    def handle_reg_abort(self, bits):
        # Bits[31:1]: reserved. Bit[0]: DAPABORT.
        a = '' if (bits[0] == '1') else 'No '
        s = 'DAPABORT = %s: %sDAP abort generated' % (bits[0], a)
        self.put(self.ss, self.es, self.out_ann, [0, [s]])

        # Warn if DAPABORT[31:1] contains non-zero bits.
        if (bits[:-1] != ('0' * 31)):
            self.put(self.ss, self.es, self.out_ann,
                     [0, ['WARNING: DAPABORT[31:1] reserved!']])

    def handle_reg_unknown(self, bits):
        self.put(self.ss, self.es, self.out_ann,
                 [0, ['Unknown instruction: ' % bits]]) # TODO

    def decode(self, ss, es, data):
        # Assumption: The right-most char in the 'val' bitstring is the LSB.
        cmd, val = data

        self.ss, self.es = ss, es

        # self.put(self.ss, self.es, self.out_ann, [0, [cmd + ' / ' + val]])

        # State machine
        if self.state == 'IDLE':
            # Wait until a new instruction is shifted into the IR register.
            if cmd != 'IR TDI':
                return
            # Switch to the state named after the instruction, or 'UNKNOWN'.
            self.state = ir.get(val[-4:], ['UNKNOWN', 0])[0]
            self.put(self.ss, self.es, self.out_ann, [0, ['IR: ' + self.state]])
        elif self.state in ('BYPASS'):
            # In these states we're interested in incoming bits (TDI).
            if cmd != 'DR TDI':
                return
            handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
            handle_reg(val)
            self.state = 'IDLE'
        elif self.state in ('IDCODE', 'DPACC', 'APACC', 'ABORT', 'UNKNOWN'):
            # In these states we're interested in outgoing bits (TDO).
            if cmd != 'DR TDO':
            # if cmd not in ('DR TDI', 'DR TDO'):
                return
            handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
            handle_reg(val)
            self.state = 'IDLE'
        else:
            raise Exception('Invalid state: %s' % self.state)
Commit	Line	Data
66a8517e UH	1	##
	2	## This file is part of the sigrok project.
	3	##
	4	## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	# ST STM32 JTAG protocol decoder
	22
	23	import sigrokdecode as srd
	24
	25	# JTAG debug port data registers (in IR[3:0]) and their sizes (in bits)
457acc28 UH	26	# Note: The ARM DAP-DP is not IEEE 1149.1 (JTAG) compliant (as per ARM docs),
	27	# as it does not implement the EXTEST, SAMPLE, and PRELOAD instructions.
	28	# Instead, BYPASS is decoded for any of these instructions.
66a8517e UH	29	ir = {
	30	'1111': ['BYPASS', 1], # Bypass register
	31	'1110': ['IDCODE', 32], # ID code register
	32	'1010': ['DPACC', 35], # Debug port access register
	33	'1011': ['APACC', 35], # Access port access register
e9656a0c	34	'1000': ['ABORT', 35], # Abort register # TODO: 32 bits? Datasheet typo?
66a8517e UH	35	}
	36
	37	# ARM Cortex-M3 r1p1-01rel0 ID code
	38	cm3_idcode = 0x3ba00477
	39
	40	# JTAG ID code in the STM32F10xxx BSC (boundary scan) TAP
	41	jtag_idcode = {
	42	0x06412041: 'Low-density device, rev. A',
	43	0x06410041: 'Medium-density device, rev. A',
	44	0x16410041: 'Medium-density device, rev. B/Z/Y',
	45	0x06414041: 'High-density device, rev. A/Z/Y',
	46	0x06430041: 'XL-density device, rev. A',
	47	0x06418041: 'Connectivity-line device, rev. A/Z',
	48	}
	49
	50	# ACK[2:0] in the DPACC/APACC registers
	51	ack_val = {
	52	'000': 'Reserved',
	53	'001': 'WAIT',
	54	'010': 'OK/FAULT',
	55	'011': 'Reserved',
	56	'100': 'Reserved',
	57	'101': 'Reserved',
	58	'110': 'Reserved',
	59	'111': 'Reserved',
	60	}
	61
	62	# 32bit debug port registers (addressed via A[3:2])
	63	reg = {
	64	'00': 'Reserved', # Must be kept at reset value
	65	'01': 'DP CTRL/STAT',
	66	'10': 'DP SELECT',
	67	'11': 'DP RDBUFF',
	68	}
	69
e9656a0c UH	70	# TODO: All start/end sample values in self.put() calls are bogus.
e9656a0c UH	71
457acc28 UH	72	# Bits[31:28]: Version (here: 0x3)
	73	# JTAG-DP: 0x3, SW-DP: 0x2
	74	# Bits[27:12]: Part number (here: 0xba00)
	75	# JTAG-DP: 0xba00, SW-DP: 0xba10
	76	# Bits[11:1]: JEDEC (JEP-106) manufacturer ID (here: 0x23b)
	77	# Bits[11:8]: Continuation code ('ARM Limited': 0x04)
	78	# Bits[7:1]: Identity code ('ARM Limited': 0x3b)
	79	# Bits[0:0]: Reserved (here: 0x1)
	80	def decode_device_id_code(bits):
	81	id_hex = '0x%x' % int('0b' + bits, 2)
	82	ver = '0x%x' % int('0b' + bits[-32:-28], 2)
	83	part = '0x%x' % int('0b' + bits[-28:-12], 2)
	84	manuf = '0x%x' % int('0b' + bits[-12:-1], 2)
	85	res = '0x%x' % int('0b' + bits[-1], 2)
	86	return (id_hex, ver, part, manuf, res)
	87
66a8517e UH	88	class Decoder(srd.Decoder):
	89	api_version = 1
	90	id = 'jtag_stm32'
	91	name = 'JTAG / STM32'
	92	longname = 'Joint Test Action Group / ST STM32'
	93	desc = 'ST STM32-specific JTAG protocol.'
	94	license = 'gplv2+'
	95	inputs = ['jtag']
	96	outputs = ['jtag_stm32']
	97	probes = []
	98	optional_probes = []
	99	options = {}
	100	annotations = [
e9656a0c	101	['Text', 'Human-readable text'],
66a8517e UH	102	]
	103
	104	def __init__(self, **kwargs):
	105	self.state = 'IDLE'
e9656a0c	106	# self.state = 'BYPASS'
66a8517e UH	107
	108	def start(self, metadata):
	109	# self.out_proto = self.add(srd.OUTPUT_PROTO, 'jtag_stm32')
	110	self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag_stm32')
	111
	112	def report(self):
	113	pass
	114
	115	def handle_reg_bypass(self, bits):
	116	# TODO
e9656a0c	117	self.put(self.ss, self.es, self.out_ann, [0, ['BYPASS: ' + bits]])
66a8517e UH	118
	119	def handle_reg_idcode(self, bits):
	120	# TODO
e9656a0c	121	self.put(self.ss, self.es, self.out_ann,
457acc28 UH	122	[0, ['IDCODE: %s (ver=%s, part=%s, manuf=%s, res=%s)' % \
457acc28 UH	123	decode_device_id_code(bits)]])
66a8517e UH	124
	125	# When transferring data IN:
	126	# Bits[34:3] = DATA[31:0]: 32bit data to transfer (write request)
	127	# Bits[2:1] = A[3:2]: 2-bit address of a debug port register
	128	# Bits[0:0] = RnW: Read request (1) or write request (0)
	129	# When transferring data OUT:
	130	# Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
	131	# Bits[2:0] = ACK[2:0]: 3-bit acknowledge
	132	def handle_reg_dpacc(self, bits):
e9656a0c UH	133	self.put(self.ss, self.es, self.out_ann, [0, ['DPACC: ' + bits]])
	134
	135	# TODO: When to use Data IN / Data OUT?
66a8517e UH	136
66a8517e UH	137	# Data IN
e9656a0c UH	138	data, a, rnw = bits[:-3], bits[-3:-1], bits[-1]
e9656a0c UH	139	data_hex = '0x%x' % int('0b' + data, 2)
66a8517e	140	r = 'Read request' if (rnw == '1') else 'Write request'
e9656a0c	141	s = 'DATA: %s, A: %s, RnW: %s' % (data_hex, reg[a], r)
66a8517e UH	142	self.put(self.ss, self.es, self.out_ann, [0, [s]])
	143
	144	# Data OUT
e9656a0c UH	145	data, ack = bits[:-3], bits[-3:]
	146	data_hex = '0x%x' % int('0b' + data, 2)
	147	ack_meaning = ack_val[ack]
	148	s = 'DATA: %s, ACK: %s' % (data_hex, ack_meaning)
	149	self.put(self.ss, self.es, self.out_ann, [0, [s]])
66a8517e	150
e9656a0c UH	151	# When transferring data IN:
	152	# Bits[34:3] = DATA[31:0]: 32bit data to shift in (write request)
	153	# Bits[2:1] = A[3:2]: 2-bit address (sub-address AP register)
	154	# Bits[0:0] = RnW: Read request (1) or write request (0)
	155	# When transferring data OUT:
	156	# Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
	157	# Bits[2:0] = ACK[2:0]: 3-bit acknowledge
66a8517e	158	def handle_reg_apacc(self, bits):
e9656a0c UH	159	self.put(self.ss, self.es, self.out_ann, [0, ['APACC: ' + bits]])
	160
	161	# TODO: When to use Data IN / Data OUT?
	162
	163	# Data IN
	164	data, a, rnw = bits[:-3], bits[-3:-1], bits[-1]
	165	data_hex = '0x%x' % int('0b' + data, 2)
	166	r = 'Read request' if (rnw == '1') else 'Write request'
	167	s = 'DATA: %s, A: %s, RnW: %s' % (data_hex, reg[a], r)
	168	self.put(self.ss, self.es, self.out_ann, [0, [s]])
	169
	170	# Data OUT
	171	data, ack = bits[:-3], bits[-3:]
	172	data_hex = '0x%x' % int('0b' + data, 2)
	173	ack_meaning = ack_val[ack]
	174	s = 'DATA: %s, ACK: %s' % (data_hex, ack_meaning)
	175	self.put(self.ss, self.es, self.out_ann, [0, [s]])
66a8517e UH	176
	177	def handle_reg_abort(self, bits):
	178	# Bits[31:1]: reserved. Bit[0]: DAPABORT.
	179	a = '' if (bits[0] == '1') else 'No '
	180	s = 'DAPABORT = %s: %sDAP abort generated' % (bits[0], a)
	181	self.put(self.ss, self.es, self.out_ann, [0, [s]])
	182
e9656a0c	183	# Warn if DAPABORT[31:1] contains non-zero bits.
66a8517e	184	if (bits[:-1] != ('0' * 31)):
e9656a0c UH	185	self.put(self.ss, self.es, self.out_ann,
	186	[0, ['WARNING: DAPABORT[31:1] reserved!']])
	187
	188	def handle_reg_unknown(self, bits):
	189	self.put(self.ss, self.es, self.out_ann,
	190	[0, ['Unknown instruction: ' % bits]]) # TODO
66a8517e UH	191
	192	def decode(self, ss, es, data):
	193	# Assumption: The right-most char in the 'val' bitstring is the LSB.
	194	cmd, val = data
	195
	196	self.ss, self.es = ss, es
	197
e9656a0c	198	# self.put(self.ss, self.es, self.out_ann, [0, [cmd + ' / ' + val]])
66a8517e UH	199
66a8517e UH	200	# State machine
e9656a0c UH	201	if self.state == 'IDLE':
	202	# Wait until a new instruction is shifted into the IR register.
	203	if cmd != 'IR TDI':
	204	return
	205	# Switch to the state named after the instruction, or 'UNKNOWN'.
	206	self.state = ir.get(val[-4:], ['UNKNOWN', 0])[0]
	207	self.put(self.ss, self.es, self.out_ann, [0, ['IR: ' + self.state]])
	208	elif self.state in ('BYPASS'):
	209	# In these states we're interested in incoming bits (TDI).
	210	if cmd != 'DR TDI':
	211	return
	212	handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
	213	handle_reg(val)
	214	self.state = 'IDLE'
	215	elif self.state in ('IDCODE', 'DPACC', 'APACC', 'ABORT', 'UNKNOWN'):
	216	# In these states we're interested in outgoing bits (TDO).
457acc28 UH	217	if cmd != 'DR TDO':
457acc28 UH	218	# if cmd not in ('DR TDI', 'DR TDO'):
e9656a0c UH	219	return
	220	handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
	221	handle_reg(val)
	222	self.state = 'IDLE'
	223	else:
	224	raise Exception('Invalid state: %s' % self.state)
66a8517e	225