Search results

# Enter a title, e.g. "Deploy key for sigrok-sync" == Add private key to the source repository (<code>sigrok-sync</code>) ==

usb: "SYNC INVALID!" "001001001100100" usb: "SYNC INVALID!" "000000000000110000000111111100100000000010001"

* Cypress CY7C1480V33-200AXC (72Mbit pipelined sync SRAM, 200MHz)

* Sync signal output is connected without any buffer or amplifier. * bit 12 controls the "sync out" port: 1 is on, 0 is off

* Cypress CY7C1347G-250AXC (4Mbit pipelined sync SRAM, 250MHz)

* Cypress CY7C1347G-250AXC (4Mbit pipelined sync SRAM, 250MHz)

bit 3 - unknown USBXI sync trigger config, default: 1 bit 4 - unknown USBXI sync trigger config, default: 0

* Cypress pipelined sync SRAM, varies by model:

...n FTDI FT232H chip (we use libftdi to talk to it) that gets configured to "Sync FIFO" mode by the software, allowing theoretical transfer speeds up to 40 M ...IFO" mode, by first resetting the so-called "bitmode", then setting it to "Sync FIFO" (as per FTDI datasheet).

The sync byte (23th) is Line Feed; LF, <source enclose="none">0x0A</source>, <source

...atasheet ICS570BL] (IDT, "multiplier and zero delay buffer", trigger clock sync?)

'''Note''': Idea how sync 2 chips works. Second FX2 is responsible for reading ADC data only, but it

* Signal if we are currently capturing using some unused pin (= sync multiple analyzers together using triggers!) [https://github.com/gillham/lo

#'''OUTPut:SYNC OFF'''

(i.e. there's no defined sync method other that reconnection).

{{pd|parallel|Parallel|Parallel sync bus|Generic parallel synchronous bus.|Util|logic|parallel|supported}}