XZL_Studio DX

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XZL_Studio DX
Status planned
Source code fx2lafw
Channels 16 + 2
Samplerate 24MHz
Samplerate (state)
Triggers none (SW-only)
Min/max voltage Digital 0 — 5.4V
Analog ±10V
Threshold voltage Fixed: VIH=1.4V, VIL=0.8V
Memory none
Compression none
Website hotmcu.com

The XZL_Studio DX is a USB-based, 16-channel logic analyzer with up to 24MHz sampling rate, and with 2 additional analog channels.

It is a clone of the CWAV USBee DX.

See XZL_Studio DX/Info for some more details (such as lsusb -vvv output) on the device.

Note: Due to the fact that this device has two FX2 chips behind a USB hub inside, this will need extra code to enumerate correctly in sigrok. Do you have this device? Let us know!

Hardware

Two jumpers:

  • P1 jumper - WRITE PROTECT, Connects WP EEPROM pin [7] to Vcc. If pin is closed, Write Protection is enabled.
  • P3 jumper - EEPROM CONNECTION, connects SDA EEPROM pin [5] to some pin on second CY7C68013A (if open there is no connection)

Extra info,
It looks that place for second eeprom is designed as backup memory. If P4 is closed, and P3 is open, then only spare memory is connected.


Pin mapping

First CY7C68013A
Responsible for all digital inputs (0-15). Now it works with latest software version, but channels are mixed:

# Input Connected to (via resistor)
0 FD4
1 FD5
2 FD6
3 FD7
4 FD3
5 FD2
6 FD1
7 FD0
8 FD15
9 FD14
a FD13
b FD8
c FD9
d FD10
e FD11
f FD12
TRIG pin CTL0/FLAGA


Second CY7C68013A

Connected to both ADCs
FX2LP pin mappings

# EEPROM Processor
Pin Desitination for CH1 Desitination for CH2 Remark
CLS RDY1/SLWR RDY1/SLWR ADC_clock
D1-D8 FD0-FD7 FD8-DF15 ADC_data


EEPROM - connected to both (!) CY7C68013A processors

# EEPROM Processor
SDA SDA via jumper
SDC SDC

TODO

Photos

Protocol

Since we use the open-source fx2lafw firmware for this device, we don't need to know the protocol.

Resources

TODO.