Difference between revisions of "LeCroy LogicStudio"

From sigrok
Jump to navigation Jump to search
(Add photos of the FPGA and FX2)
Line 15: Line 15:
}}
}}


The '''LeCroy LogicStudio''' is an USB logic analyzer with 16 channels that offers up to 1GHz samplerate. When all 16 channels are enabled, the maximum samplerate is limited to at most 500MHz. Either the lower eight or the upper eight channels may be disabled for an increased samplerate of up to 1GHz. The device offers a continuous acquisition mode where all inputs are sampled at a frequency of 1kHz.
The '''LeCroy LogicStudio''' is an USB logic analyzer with 16 channels that offers up to 1GHz samplerate. When all 16 channels are enabled, the maximum samplerate is limited to at most 500MHz. Either the lower eight or the upper eight channels may be disabled for an increased samplerate of up to 1GHz. The device offers a continuous acquisition mode where all inputs are sampled at a frequency of 1kHz. Its internal protocol decoder supports UART, I2C and SPI.


== Hardware ==
== Hardware ==
* '''FPGA''': Xilinx Spartan-6 XC6SLX16
* '''FPGA''': Xilinx Spartan-6 XC6SLX16
* '''USB interface''':  [http://www.cypress.com/?docID=45142 Cypress CY7C68013A]
* '''USB interface''':  [http://www.cypress.com/?docID=45142 Cypress CY7C68013A]
* '''Crystal (FX2):''' 24.000MHz
* '''Crystal (FX2LP):''' 24.000MHz
* '''Crystal (FPGA):''' Unknown, xpress0?
* '''Crystal (FPGA):''' Unknown, xpress0?


Line 30: Line 30:
File:Lecroy-logicstudio-usb.jpg|<small>FX2</small>
File:Lecroy-logicstudio-usb.jpg|<small>FX2</small>
</gallery>
</gallery>
== Trigger Capabilities ==
The device has both standard logic triggers as well as triggers that operate on data produced by its internal protocol decoder.
There are two logic trigger blocks A and B which can optionally be combined in the following ways:
* A AND B
* A OR B
* A THEN B
Each logic trigger block offers the following match criteria:
* Rising edge
* Falling edge
* Any edge
* Level 0 (including pulse width)
* Level 1 (ditto)
* Qualified edge triggers (trigger on rising/falling/any edge while another signal is high/low).
Multiple edge triggers in the same block are OR'd, while multiple level triggers in the same block are AND'ed.
Each trigger block can further be configured with a number of times that the trigger criteria need to match before the trigger fired.
== Internals ==
The device initially shows up as VID:PID 0x5ff:0xa001 on the USB bus. It then requires a firmware upload to its FX2LP chip, after which the original USB device disappears and a new one shows up, with VID:PID 0x5ff:0xa002.
The bitstreams for the FPGA come in two versions: one which enables all 16 channels, and one which only enables either the bottom 8 or the top 8 channels. If the first bitstream is uploaded, the maximum allowed sample rate is 500MHz. If the second bitstream is uploaded, the device can sample at up to 1GHz. In the latter case, a separate command seems to control whether the lower or the upper channels are enabled.

Revision as of 19:47, 14 October 2015

LeCroy LogicStudio
Lecroy-logicstudio.jpg
Status
Channels 16
Samplerate up to 1GHz (when sampling 8 channels) ; up to 500MHz (when sampling 16 channels)
Samplerate (state)
Triggers high/low state, rising/falling/any edge, more
Min/max voltage ?
Threshold voltage ?
Memory ?
Compression none
Website teledynelecroy.com

The LeCroy LogicStudio is an USB logic analyzer with 16 channels that offers up to 1GHz samplerate. When all 16 channels are enabled, the maximum samplerate is limited to at most 500MHz. Either the lower eight or the upper eight channels may be disabled for an increased samplerate of up to 1GHz. The device offers a continuous acquisition mode where all inputs are sampled at a frequency of 1kHz. Its internal protocol decoder supports UART, I2C and SPI.

Hardware

  • FPGA: Xilinx Spartan-6 XC6SLX16
  • USB interface: Cypress CY7C68013A
  • Crystal (FX2LP): 24.000MHz
  • Crystal (FPGA): Unknown, xpress0?

Photos

Trigger Capabilities

The device has both standard logic triggers as well as triggers that operate on data produced by its internal protocol decoder. There are two logic trigger blocks A and B which can optionally be combined in the following ways:

  • A AND B
  • A OR B
  • A THEN B

Each logic trigger block offers the following match criteria:

  • Rising edge
  • Falling edge
  • Any edge
  • Level 0 (including pulse width)
  • Level 1 (ditto)
  • Qualified edge triggers (trigger on rising/falling/any edge while another signal is high/low).

Multiple edge triggers in the same block are OR'd, while multiple level triggers in the same block are AND'ed. Each trigger block can further be configured with a number of times that the trigger criteria need to match before the trigger fired.

Internals

The device initially shows up as VID:PID 0x5ff:0xa001 on the USB bus. It then requires a firmware upload to its FX2LP chip, after which the original USB device disappears and a new one shows up, with VID:PID 0x5ff:0xa002.

The bitstreams for the FPGA come in two versions: one which enables all 16 channels, and one which only enables either the bottom 8 or the top 8 channels. If the first bitstream is uploaded, the maximum allowed sample rate is 500MHz. If the second bitstream is uploaded, the device can sample at up to 1GHz. In the latter case, a separate command seems to control whether the lower or the upper channels are enabled.