|Samplerate (state)||State analysis not supported|
Level (multiple channels)|
Edge (one channel)
|Min/max voltage||-50V — 50V|
-4V—4V, min step 0.01V
128MByte DDR2 SDRAM|
The Kingst LA2016 is a USB-based, 16-channel logic analyser with 200MHz maximum sampling rate. The current vendor is "Qingdao Kingst Electronics Co., Ltd." but older models are branded "Jiankun" rather than "Kingst". The vendor software can be freely downloaded from their website.
See Kingst LA2016/Info for more details (such as lsusb -v output) about the device.
2021-03-30 status: This device is basically supported, captures can be made. But some important features still are not available or not fully operational. It's yet to get determined what these features are that currently don't work as intended. (This wiki page needs an update so that users can determine whether _their_ use case is covered.)
2021-07-13 status: Some users are reporting this device does not function with PulseView. In this case, please try these PRs:
This logic analyser has been on the market since around 2012 and there are a few different revisions of it. The schematic has been reverse engineered from a unit purchased in 2020 containing a PCB marked as v1.3.0. The circuitry of older PCBs is similar but may have different voltage regulators, different input channel routing to the FPGA, and lack the input threshold adjustment.
The LA1016 uses identical hardware with a different FPGA bitstream which limits the sample rate to 100MHz maximum.
All of these devices use the same firmware for the FX2LP MCU but there are four different FPGA bitstreams; i.e. LA1016 & LA2016 bitstreams and the older versions of these (to swap some of the input channels as required by PCB routing changes). Once the FX2LP firmware has been loaded, a 'magic number' is read from EEPROM which identifies the device and thus allows the correct FPGA bitstream to be loaded.
Note that the LA1016 cannot be boosted to 200MHz by changing the 'magic number' or the FPGA bitstream. When the FPGA initialises, its reads 16 bytes from U10 which are used to authenticate the bitstream; these bytes are different for 100 and 200MHz devices. Furthermore, the OEM software performs a challenge-response with U10 to authenticate the logic analyser as genuine 'Kingst'. The good news is that U10 does not impact sigrok support in any way and we don't need to communicate with it.
Main components and their function:
- MCU Cypress FX2LP
- This MCU only has volatile memory and in this implementation it's firmware is loaded from the host by the application software.
- Either the OEM firmware or open source firmware can be used.
- In essence, it just performs data moving operations:
- Endpoint 0 to EEPROM read/write
- Endpoint 0 to SPI read/write for FPGA control registers
- Endpoint 2 bulk out to SPI for loading FPGA bitstream
- Endpoint 6 bulk in to read capture data from FPGA/SDRAM
- EEPROM Atmel AT24C02 2Kbit
- This non-volatile memory stores:
- VID:PID which is 77a1:01a2 for LA1016 and LA2016 devices
- 'magic number' to identify model and revision
- purchase date (presumably for warranty claims)
- other information related to U10 but not of interest to sigrok
- FPGA Altera EP4CE6
- Currently requires the OEM bitstream.
- Has a bank of approximately 60 byte-wide registers accessed via SPI which are used to contol FPGA functions.
- Captures 16 input channels, performs compression (run length encoding, 16bit sample plus 8 bit repetition count).
- Stores samples to SDRAM (or streams direct to USB but we don't implement that method).
- Interestingly, this device (6K LE) shares the same die as the next up device EP4CE10 (10K LE) and can be programmed as such. However, functionality would not be guaranteed as CE6 devices may be CE10 rejects.
- If open source FPGA code were to become available there would be capacity to experiment with more advanced triggers, such as pattern trigger for SPI or I2C.
- SDRAM Samsung DDR2
- Samples are stored as 3 bytes (16bit sample plus 8 bit repetition count).
- A 'transfer packet' for upload is 16 bytes = 5 compressed samples plus a sequence number byte.
- Burst read/write for this SDRAM is up to 16 bytes, which matches the transfer packet size and is likely used for all SDRAM read/writes.
- U10 Kingst Authentication Device
- Not used by sigrok.
- Provides fixed bytes identifier to FPGA for bitstream validation (either LA1016 100MHz or LA2016 200MHz bitstream)
- Provides challenge-response rolling-code for OEM software to authenticate the device as genuine 'Kingst'
- U1 EP4CE6F17C8N Cyclone IV E FPGA
- U2,4,5,7 PDWL050019 TVS Diode Array
- U3 CY7C68013A-100AXC EZUSB MCU
- U6,U8 SGM2019 Linear Regulator
- U9 AT24C02 EEPROM 2kbit
- U10 (device not identified, small MCU of some type)
- U11 K4T1G164QG-BCF8, DDR2 SDRAM, obsolete
- U12,U13 SGM6013 Switch-mode Regulator
- U14 SGM8272 Dual Op-amp
- U15 TPS60403 Charge Pump Voltage Inverter
TODO This extraction script needs an update
In order to use this device you need to extract the firmware/FPGA files from the vendor software (Linux download) using the sigrok-fwextract-kingst-la2016 script from the sigrok-util repo and place them in one of the usual places where libsigrok expects firmware files:
$ ./sigrok-fwextract-kingst-la2016 KingstVIS/KingstVIS saved 180224 bytes to kingst-la2016a-fpga.bitstream saved 5350 bytes to kingst-la-01a1.fw saved 5430 bytes to kingst-la-01a2.fw saved 5718 bytes to kingst-la-01a3.fw saved 142412 bytes to kingst-la-01a4.fw saved 5452 bytes to kingst-la-03a1.fw