Difference between revisions of "Main Page"
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File:Saleae Logic.jpg|<small>'''[[Saleae Logic]]'''<br />(supported)</small> | File:Saleae Logic.jpg|<small>'''[[Saleae Logic]]'''<br />(supported)</small> | ||
File:Eeelec xla esla100.jpg|<small>'''[[EE Electronics XLA ESLA100|EE Electronics XLA/ESLA100]]''' (supported)</small> | File:Eeelec xla esla100.jpg|<small>'''[[EE Electronics XLA ESLA100|EE Electronics XLA/ESLA100]]''' (supported)</small> | ||
File: | File:ASIX SIGMA.jpg|<small>'''[[ASIX SIGMA]]''' (partially supported)</small> | ||
File:Open workbench logic sniffer.jpg|<small>'''[[Openbench Logic Sniffer]]'''<br />(work in progress)</small> | File:Open workbench logic sniffer.jpg|<small>'''[[Openbench Logic Sniffer]]'''<br />(work in progress)</small> | ||
File:Zeroplus Logic Cube.jpg|<small>'''[[ZEROPLUS Logic Cube LAP-C]]''' (work in progress)</small> | File:Zeroplus Logic Cube.jpg|<small>'''[[ZEROPLUS Logic Cube LAP-C]]''' (work in progress)</small> |
Revision as of 18:36, 28 April 2010
The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source logic analyzer software that supports various (usually USB-based) logic analyzer hardware products. The code is licensed under the terms of the GNU GPL. Design goals
Supported hardware
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