Difference between revisions of "Protocol decoder:Iebus"
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The protocol capture can be performed with a comparator circuit connected to 4 resistors: | The protocol capture can be performed with a comparator circuit connected to 4 resistors: | ||
[[File:Iebus-sniffer.png|400px]] | |||
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== Protocol == | == Protocol == | ||
The protocol itself has been documented pretty extensively on [https://en.wikipedia.org/wiki/IEBus Wikipedia] as well as other more | |||
niche pages: | |||
[http://softservice.com.pl/corolla/avc/avclan.php] | |||
[https://elinux.org/AVC-LAN] | |||
[http://www.interfacebus.com/Design_Connector_IEbus.html] | |||
AVC-LAN operates in IEBus Mode 2 which means that the time for each bit is 39µs. | |||
The example scope trace below provides an overview of the voltages and timings that with which the bus operates: | |||
[[File:Iebus-mode2-frame.png]] | |||
Each frame begins with a start bit: | |||
[[File:Iebus-mode2-startbit-annotated.png]] | |||
which is followed by a number of data bits where each bit can be synchronized by a raising edge, a synchronization period and a data period. This is highlighed in the trace below: | |||
[[File:Iebus-mode2-sync-annotated.png]] | |||
In practice the decoder implementation waits for the sync period to expire and then samples the bus to probe which bit is being transmitted. An alternative approach can be also used where a decoder can measure the pulse length between the rising synchronization edge and the falling edge before the next bit is being transmitted. The below traces provide a comparison between what happens on the bus when 0 and 1 are being transmitted: | |||
[[File:Iebus-mode2-bit0-annotated.png]] | |||
[[File:Iebus-mode2-bit1-annotated.png]] | |||
== Resources == | == Resources == | ||
Revision as of 13:55, 7 June 2023
| Name | IEBus |
|---|---|
| Description | A multidrop differential CAN-like bus used in multimedia applications. |
| Status | 100% |
| License | GPLv3+ |
| Source code | decoders/ |
| Input | logic |
| Output | iebus |
| Probes | — |
| Optional probes | ? |
| Options | — |
The iebus protocol decoder...
Hardware
The protocol capture can be performed with a comparator circuit connected to 4 resistors:
Photos:
TODO.
Protocol
The protocol itself has been documented pretty extensively on Wikipedia as well as other more niche pages: [1] [2] [3]
AVC-LAN operates in IEBus Mode 2 which means that the time for each bit is 39µs.
The example scope trace below provides an overview of the voltages and timings that with which the bus operates:
Each frame begins with a start bit:
which is followed by a number of data bits where each bit can be synchronized by a raising edge, a synchronization period and a data period. This is highlighed in the trace below:
In practice the decoder implementation waits for the sync period to expire and then samples the bus to probe which bit is being transmitted. An alternative approach can be also used where a decoder can measure the pulse length between the rising synchronization edge and the falling edge before the next bit is being transmitted. The below traces provide a comparison between what happens on the bus when 0 and 1 are being transmitted:
Resources
- TODO.