Difference between revisions of "DreamSourceLab DSLogic Plus"

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(→‎Photos: Add pcb photos. Note: image of back side is mirrored.)
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== Hardware ==
== Hardware ==
* [http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/ Xilinx XC6SLX9] U3: Spartan-6 FPGA (TQG144BIV13337)
* [https://www.alliancememory.com/wp-content/uploads/pdf/dram/256Mb-AS4C16M16SA-C&I_V3.0_March%202015.pdf Alliance AS4C16M16SA-7TCN] U1: 256Mbit SDRAM
* [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A] U2: FX2LP USB interface chip
* [http://www.st.com/content/ccc/resource/technical/document/datasheet/59/05/c9/5b/7b/41/48/b6/CD00259167.pdf/files/CD00259167.pdf/jcr:content/translations/en.CD00259167.pdf 128Kbit I²C EEPROM] U4: ST M24128-BR
* Unknown DC-DC U10: 3.3V and 1.2V output, 2.4Mhz (markings: BQE 791 C7JS)
* [http://file1.jzsc8.com/mallpropdf/16/04/28/151237988.pdf 24.0Mhz Crystal] Y1: [http://www.yxc.hk/u_file/product/17_08_22/YSX321SL.pdf YSX321SL series] 20ppm (markings: YXC 24.0SBJI)


== Photos ==
== Photos ==

Revision as of 22:48, 13 February 2018

DreamSourceLab DSLogic Plus
DSLogic.png
Status supported
Source code dreamsourcelab-dslogic
Channels 1-16
Samplerate 400MHz(4ch), 200MHz(8ch), 100MHz(16ch)
Samplerate (state) 30MHz (?) or 50MHz (?)
Triggers high, low, rising, falling, edge, multi-stage triggers
Min/max voltage -0.6V — 6V
Threshold voltage configurable: 0-5V (0.1V increments)
Memory 32MByte (2MByte/ch)
Compression yes
Website dreamsourcelab.com

The DreamSourceLab DSLogic Plus is a 16-channel USB-based logic analyzer, with sampling rates up to 400MHz (when using only 4 channels). This differs slightly from the original DSLogic product in its configurable threshold voltage and different PCB layout. DreamSourceLab doesn't make the distinction between these two products very clear on their website.

See DreamSourceLab DSLogic Plus/Info for more details (such as lsusb -v output) about the device.

Hardware

Photos

Device:

Cables:

Firmware

See DreamSourceLab DSLogic#Firmware.

Resources