Difference between revisions of "Sysclk LWLA1016"
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| status = in progress | | status = in progress | ||
| source_code_dir = | | source_code_dir = | ||
| channels = 16 | | channels = 16/8 | ||
| samplerate = | | samplerate = 100/200/250 MHz | ||
| samplerate_state = ? | | samplerate_state = ? | ||
| triggers = | | triggers = only in 100MHz mode | ||
| voltages = ? | | voltages = ? | ||
| threshold = ? | | threshold = ? | ||
| memory = 256Kbit/channel | | memory = 256Kbit/channel | ||
| compression = | | compression = optional | ||
| website = [http://item.taobao.com/item.htm?id=12821371102 taobao.com] | | website = [http://item.taobao.com/item.htm?id=12821371102 taobao.com] | ||
}} | }} | ||
Revision as of 10:22, 6 July 2015
 | |
| Status | in progress |
|---|---|
| Channels | 16/8 |
| Samplerate | 100/200/250 MHz |
| Samplerate (state) | ? |
| Triggers | only in 100MHz mode |
| Min/max voltage | ? |
| Threshold voltage | ? |
| Memory | 256Kbit/channel |
| Compression | optional |
| Website | taobao.com |
The Sysclk LWLA1016 is a USB-based, 16-channel logic analyzer with up to 100MHz sampling rate, or up to 250MHz with 8 channels.
See Sysclk LWLA1016/Info for more details (such as lsusb -v output) about the device.
Hardware
TODO.
Photos
Device, front
Device, back
Device, open
PCB, top
PCB, bottom
Cypress FX2
ISSI 1
ISSI 2
ATMLH105
STC
LDOs
Input stage
Crystal
Protocol
Reverse engineering of the vendor's custom protocol has begun. See Sysclk LWLA1016/Protocol for the findings gathered so far.
Resources
TODO.