Difference between revisions of "DreamSourceLab DSLogic Plus"
Jump to navigation
Jump to search
Reversebias (talk | contribs) (Including hardware information about a new V421 variant.) |
|||
| (8 intermediate revisions by 3 users not shown) | |||
| Line 8: | Line 8: | ||
| samplerate_state = 30MHz (?) or 50MHz (?) | | samplerate_state = 30MHz (?) or 50MHz (?) | ||
| triggers = high, low, rising, falling, edge, multi-stage triggers | | triggers = high, low, rising, falling, edge, multi-stage triggers | ||
| voltages = -0.6V — 6V | | voltages = -0.6V — 6V, +-30V with provided probe-wires | ||
| threshold = configurable: 0-5V (0.1V increments) | | threshold = configurable: 0-5V (0.1V increments) | ||
| memory = | | memory = 256MBit | ||
| compression = yes | | compression = yes | ||
| website = [http://www.dreamsourcelab.com/dslogic.html dreamsourcelab.com] | | website = [http://www.dreamsourcelab.com/dslogic.html dreamsourcelab.com] | ||
| Line 22: | Line 22: | ||
* [http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/ Xilinx XC6SLX9] U3: Spartan-6 FPGA (TQG144BIV13337) | * [http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/ Xilinx XC6SLX9] U3: Spartan-6 FPGA (TQG144BIV13337) | ||
* [https://www.alliancememory.com/wp-content/uploads/pdf/dram/256Mb-AS4C16M16SA-C&I_V3.0_March%202015.pdf Alliance AS4C16M16SA-7TCN] U1: 256Mbit SDRAM | * Sample memory: | ||
** Original version: [https://www.alliancememory.com/wp-content/uploads/pdf/dram/256Mb-AS4C16M16SA-C&I_V3.0_March%202015.pdf Alliance AS4C16M16SA-7TCN] U1: 256Mbit SDRAM | |||
** V211: [https://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/256Mb_sdr.pdf Micron MT48LC16M16A2 256Mbit SDRAM] | |||
* [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A] U2: FX2LP USB interface chip | * [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A] U2: FX2LP USB interface chip | ||
* [http://www.st.com/content/ccc/resource/technical/document/datasheet/59/05/c9/5b/7b/41/48/b6/CD00259167.pdf/files/CD00259167.pdf/jcr:content/translations/en.CD00259167.pdf 128Kbit I²C EEPROM] U4: ST M24128-BR | * [http://www.st.com/content/ccc/resource/technical/document/datasheet/59/05/c9/5b/7b/41/48/b6/CD00259167.pdf/files/CD00259167.pdf/jcr:content/translations/en.CD00259167.pdf 128Kbit I²C EEPROM] U4: ST M24128-BR | ||
* [http://www.ti.com/product/TPS62400 TI TPS62400] U10: Dual, Adjustable, 400mA and 600mA, 2.25MHz Step-Down Converter (3.3V and 1.2V output) | * [http://www.ti.com/product/TPS62400 TI TPS62400] U10: Dual, Adjustable, 400mA and 600mA, 2.25MHz Step-Down Converter (3.3V and 1.2V output) | ||
* [http://file1.jzsc8.com/mallpropdf/16/04/28/151237988.pdf 24.0Mhz Crystal] Y1: [http://www.yxc.hk/u_file/product/17_08_22/YSX321SL.pdf YSX321SL series] 20ppm (markings: YXC 24.0SBJI) | |||
== Hardware (V421/Pango Variant) == | |||
New hardware variant received early 2023, enumerates as 2a0e:0030, and uses a different vendor's FPGA. Currently incompatible with sigrok. | |||
* [https://www-pangomicro-com.translate.goog/procenter/detail4.html?_x_tr_sl=auto&_x_tr_tl=en&_x_tr_hl=en&_x_tr_pto=wapp PangoMicro Logos PGL12G] U13: PGL12G, 12k LUT, LPG144 package | |||
* [https://www.winbond.com/resource-files/w9825g6kh_a04.pdf Winbond W9825G6KH-6] U6: 256Mbit SDRAM | |||
* [http://www.cypress.com/?mpn=CY7C68013A-56PVXC Cypress CY7C68013A] U2: FX2LP USB interface chip | |||
* [http://www.st.com/content/ccc/resource/technical/document/datasheet/59/05/c9/5b/7b/41/48/b6/CD00259167.pdf/files/CD00259167.pdf/jcr:content/translations/en.CD00259167.pdf 128Kbit I²C EEPROM] U4: ST M24128-BR | |||
* Unmarked 3.3V and 1.2V regulators | |||
* [http://file1.jzsc8.com/mallpropdf/16/04/28/151237988.pdf 24.0Mhz Crystal] Y1: [http://www.yxc.hk/u_file/product/17_08_22/YSX321SL.pdf YSX321SL series] 20ppm (markings: YXC 24.0SBJI) | * [http://file1.jzsc8.com/mallpropdf/16/04/28/151237988.pdf 24.0Mhz Crystal] Y1: [http://www.yxc.hk/u_file/product/17_08_22/YSX321SL.pdf YSX321SL series] 20ppm (markings: YXC 24.0SBJI) | ||
| Line 34: | Line 47: | ||
File:Dslogic_plus_pcb_front.jpg|<small>PCB, front</small> | File:Dslogic_plus_pcb_front.jpg|<small>PCB, front</small> | ||
File:Dslogic_plus_pcb_back.jpg|<small>PCB, back (mirrored)</small> | File:Dslogic_plus_pcb_back.jpg|<small>PCB, back (mirrored)</small> | ||
File:Dslogic_plus_V211_pcb_front.jpeg|<small>PCB V211, front</small> | |||
File:Dslogic_plus_V211_pcb_back.jpeg|<small>PCB V211, back</small> | |||
File:Dslogic plus V421 pcb front.jpg|<small>PCB V421, front</small> | |||
File:Dslogic plus V421 pcb rear.jpg|<small>PCB V421, back</small> | |||
</gallery> | </gallery> | ||
| Line 44: | Line 62: | ||
File:Dreamsourcelab dslogic plus cable 5.jpg | File:Dreamsourcelab dslogic plus cable 5.jpg | ||
File:Dreamsourcelab dslogic plus probe circuit.png|<small>Probe cable circuit</small> | File:Dreamsourcelab dslogic plus probe circuit.png|<small>Probe cable circuit</small> | ||
File:Dreamsourcelab dslogic plus cable B xray 1.jpg|<small>Revised Probe cable</small> | |||
File:Dreamsourcelab dslogic plus cable B xray 2.jpg|<small>Revised Probe cable</small> | |||
</gallery> | </gallery> | ||
Latest revision as of 06:25, 30 March 2023
 | |
| Status | supported |
|---|---|
| Source code | dreamsourcelab-dslogic |
| Channels | 1-16 |
| Samplerate | 400MHz(4ch), 200MHz(8ch), 100MHz(16ch) |
| Samplerate (state) | 30MHz (?) or 50MHz (?) |
| Triggers | high, low, rising, falling, edge, multi-stage triggers |
| Min/max voltage | -0.6V — 6V, +-30V with provided probe-wires |
| Threshold voltage | configurable: 0-5V (0.1V increments) |
| Memory | 256MBit |
| Compression | yes |
| Website | dreamsourcelab.com |
The DreamSourceLab DSLogic Plus is a 16-channel USB-based logic analyzer, with sampling rates up to 400MHz (when using only 4 channels). This differs slightly from the original DSLogic product in its configurable threshold voltage and different PCB layout. DreamSourceLab doesn't make the distinction between these two products very clear on their website.
See DreamSourceLab DSLogic Plus/Info for more details (such as lsusb -v output) about the device.
Hardware
- Xilinx XC6SLX9 U3: Spartan-6 FPGA (TQG144BIV13337)
- Sample memory:
- Original version: Alliance AS4C16M16SA-7TCN U1: 256Mbit SDRAM
- V211: Micron MT48LC16M16A2 256Mbit SDRAM
- Cypress CY7C68013A U2: FX2LP USB interface chip
- 128Kbit I²C EEPROM U4: ST M24128-BR
- TI TPS62400 U10: Dual, Adjustable, 400mA and 600mA, 2.25MHz Step-Down Converter (3.3V and 1.2V output)
- 24.0Mhz Crystal Y1: YSX321SL series 20ppm (markings: YXC 24.0SBJI)
Hardware (V421/Pango Variant)
New hardware variant received early 2023, enumerates as 2a0e:0030, and uses a different vendor's FPGA. Currently incompatible with sigrok.
- PangoMicro Logos PGL12G U13: PGL12G, 12k LUT, LPG144 package
- Winbond W9825G6KH-6 U6: 256Mbit SDRAM
- Cypress CY7C68013A U2: FX2LP USB interface chip
- 128Kbit I²C EEPROM U4: ST M24128-BR
- Unmarked 3.3V and 1.2V regulators
- 24.0Mhz Crystal Y1: YSX321SL series 20ppm (markings: YXC 24.0SBJI)
Photos
Device:
PCB, front
PCB, back (mirrored)
PCB V211, front
PCB V211, back
PCB V421, front
PCB V421, back
Cables:
Probe cable circuit
Revised Probe cable
Revised Probe cable
Firmware
See DreamSourceLab DSLogic#Firmware.