Difference between revisions of "ASIX SIGMA / SIGMA2"

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(triggers available again, rephrase rates/triggers/compression paragraphs, discuss constraints)
 
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Many thanks to the vendor ([http://www.asix.net/ ASIX]) for providing information on the protocol used to communicate with the device and for releasing the device's firmware / FPGA bitstreams under a [http://sigrok.org/gitweb/?p=sigrok-firmware.git;a=blob;f=asix-sigma/LICENSE.Sigma license which allows us to distribute the files].
Many thanks to the vendor ([http://www.asix.net/ ASIX]) for providing information on the protocol used to communicate with the device and for releasing the device's firmware / FPGA bitstreams under a [http://sigrok.org/gitweb/?p=sigrok-firmware.git;a=blob;f=asix-sigma/LICENSE.Sigma license which allows us to distribute the files].
</em>
</em>
Notice that the device's firmware supports quite complex hardware triggers, but the software driver is limited to data pattern (values) and edge (slope) triggers. Sample rates above 50MHz further limit the number of available channels, and trigger options.


== Hardware ==
== Hardware ==


* Xilinx Spartan XC3S50
* Xilinx Spartan XC3S50 (FPGA)
* FTDI FT245RL
* FTDI FT245RL (USB UART/FIFO, includes EEPROM)
* 2x TI SN74LVC245AN
* 2x TI SN74LVC245AN (input buffer)
* MT 48LCI6MI6A2
* MT 48LC16M16A2 (32MiB DRAM)
* ...
* voltage regulation (3V3, 2V5, 1V2)
* 2x TI '04 logic (hex inverters, for level shifting)


== Photos ==
== Photos ==


=== ASIX SIGMA ===
=== ASIX SIGMA ===
<gallery>
<gallery>
File:ASIX SIGMA.jpg
File:ASIX SIGMA.jpg
File:Sigma.jpg
File:Sigma.jpg
</gallery>
</gallery>
=== ASIX SIGMA 2 ===
=== ASIX SIGMA 2 ===
<gallery>
<gallery>
File:Omega-Top.jpg
File:ASIX SIGMA 2 back.jpg
File:Omega-Bottom.jpg
File:ASIX SIGMA 2 USB.jpg
File:ASIX SIGMA 2 header.jpg
File:ASIX SIGMA 2 PCB top.jpg
File:ASIX SIGMA 2 PCB bottom.jpg
</gallery>
</gallery>


== Documentation ==
== Documentation ==


The ASIX SIGMA/SIGMA2 firmware files are generously provided by the vendor for distribution. As a result, the device works out of the box with sigrok. Trigger support has been implemented in 100MHz and 200MHz modes for rising/falling edges. In other modes, users can specify additional trigger values, listed in the table below.
The ASIX SIGMA/SIGMA2 firmware files are generously provided by the vendor for distribution. As a result, the device works out of the box with sigrok.
 
Sample rates can be:
* 200MHz or 100MHz (fixed) with special firmware, limited number of available channels
* 50MHz divided by an integer in the 1..256 range, which results in a rough range of 200kHz to 50MHz
* external clock on one of the 16 input pins, rate up to some 20MHz (gets sampled at 50MHz)
 
Trigger support is limited to basic use:
* An edge on one of the 4 (200MHz) or 8 (100MHz) input pins. Common limitation of the device firmware.
* One edge on one of the 16 (50MHz) input pins, in addition to:
* A data pattern (levels, including "don't care", up to 50MHz) across the 16 input pins.


NOTE: In 50MHz mode, the device uses an internal 8-bit integer divider. The sample rate is therefore 50MHz/n , where n = 1...256 . The table below matches sigrok's current representation and will need to be changed.
In theory up to two edge conditions on two pins could be used, but their transition had to occur in the same 20ns check interval to consider this a match, which limits the practical use of this feature.


{| border="0" style="font-size: smaller"
Pulse width, event counts, and logic combination of several combinations are not supported in trigger conditions (the hardware does, the software doesn't). External trigger (TO trigger output, TI trigger input) currently isn't supported by the software either.
|- bgcolor="#6699ff"
!Samplerate
!Number of probes
!Trigger support
|- bgcolor="#eeeeee"
| 200 kHz
| 16
| Edge of two probes, state, boolean expression<sup>1</sup>
|- bgcolor="#dddddd"
| 250 kHz
| 16
| Edge of two probes, state, boolean expression<sup>1</sup>
|- bgcolor="#eeeeee"
| 500 kHz
| 16
| Edge of two probes, state, boolean expression<sup>1</sup>
|- bgcolor="#dddddd"
| 1 MHz
| 16
| Edge of two probes, state, boolean expression<sup>1</sup>
|- bgcolor="#eeeeee"
| 5 MHz
| 16
| Edge of two probes, state, boolean expression<sup>1</sup>
|- bgcolor="#dddddd"
| 10 MHz
| 16
| Edge of two probes, state, boolean expression<sup>1</sup>
|- bgcolor="#eeeeee"
| 25 MHz
| 16
| Edge of two probes, state, boolean expression<sup>1</sup>
|- bgcolor="#dddddd"
| 50 MHz
| 16
| Edge of two probes, state, boolean expression<sup>1</sup>
|- bgcolor="#eeeeee"
| 100 MHz
| 8
| Edge of one probe
|- bgcolor="#dddddd"
| 200 MHz
| 4
| Edge of one probe
|}


<small>
The device has local memory which can hold up to 14 MiSa (14 million samples) for input signals that keep changing all the time. When input signals don't change for a number of sample points, then hardware supported RLE compression takes effect, and can reduce memory consumption by a factor of up to 8192. Which results in a best case sample memory capacity that spans 128 GiSa (128 billion samples). Rates above 50MHz increase the number of samples taken, but at the same time reduce the number of available channels.
<sup>1</sup> Boolean expression feature not implemented in sigrok yet.<br />
</small>


== Example usage ==
== Example usage ==

Latest revision as of 18:11, 1 June 2020

ASIX SIGMA / SIGMA2
ASIX SIGMA 2.png
Status supported
Source code asix-sigma
Channels 16
Samplerate 200MHz @ 4ch, 100MHz @ 8ch, 50MHz @ 16ch
Samplerate (state) 50MHz
Triggers value, edge, duration, sequence, counter, logical ops
Min/max voltage -0.3V — 5.5V
Threshold voltage Fixed: VIH=2.0V, VIL=0.8V (suitable for TTL, LVTTL, 2.7-5.5V CMOS)
Memory 32MByte (SDRAM)
Compression "real-time hardware data compression"
Website asix.net

The ASIX SIGMA/SIGMA2 is a USB-based, 16-channel logic analyzer with up to 200MHz sampling rate.

See ASIX SIGMA/Info for more details (such as lsusb -vvv output) about the device.

Many thanks to the vendor (ASIX) for providing information on the protocol used to communicate with the device and for releasing the device's firmware / FPGA bitstreams under a license which allows us to distribute the files.

Notice that the device's firmware supports quite complex hardware triggers, but the software driver is limited to data pattern (values) and edge (slope) triggers. Sample rates above 50MHz further limit the number of available channels, and trigger options.

Hardware

  • Xilinx Spartan XC3S50 (FPGA)
  • FTDI FT245RL (USB UART/FIFO, includes EEPROM)
  • 2x TI SN74LVC245AN (input buffer)
  • MT 48LC16M16A2 (32MiB DRAM)
  • voltage regulation (3V3, 2V5, 1V2)
  • 2x TI '04 logic (hex inverters, for level shifting)

Photos

ASIX SIGMA

  • ASIX SIGMA.jpg
  • Sigma.jpg

ASIX SIGMA 2

  • ASIX SIGMA 2 back.jpg
  • ASIX SIGMA 2 USB.jpg
  • ASIX SIGMA 2 header.jpg
  • ASIX SIGMA 2 PCB top.jpg
  • ASIX SIGMA 2 PCB bottom.jpg

Documentation

The ASIX SIGMA/SIGMA2 firmware files are generously provided by the vendor for distribution. As a result, the device works out of the box with sigrok.

Sample rates can be:

  • 200MHz or 100MHz (fixed) with special firmware, limited number of available channels
  • 50MHz divided by an integer in the 1..256 range, which results in a rough range of 200kHz to 50MHz
  • external clock on one of the 16 input pins, rate up to some 20MHz (gets sampled at 50MHz)

Trigger support is limited to basic use:

  • An edge on one of the 4 (200MHz) or 8 (100MHz) input pins. Common limitation of the device firmware.
  • One edge on one of the 16 (50MHz) input pins, in addition to:
  • A data pattern (levels, including "don't care", up to 50MHz) across the 16 input pins.

In theory up to two edge conditions on two pins could be used, but their transition had to occur in the same 20ns check interval to consider this a match, which limits the practical use of this feature.

Pulse width, event counts, and logic combination of several combinations are not supported in trigger conditions (the hardware does, the software doesn't). External trigger (TO trigger output, TI trigger input) currently isn't supported by the software either.

The device has local memory which can hold up to 14 MiSa (14 million samples) for input signals that keep changing all the time. When input signals don't change for a number of sample points, then hardware supported RLE compression takes effect, and can reduce memory consumption by a factor of up to 8192. Which results in a best case sample memory capacity that spans 128 GiSa (128 billion samples). Rates above 50MHz increase the number of samples taken, but at the same time reduce the number of available channels.

Example usage

An example that captures from 4 probes, for 100ms at 10MHz, with trigger condition 1:high, 2:rising, 3:low, 4:high. 

$ sigrok-cli --driver asix-sigma --config samplerate=10m --wait-trigger \
  --triggers 1=1,2=r,3=0,4=1 --output-format bits --probes 1-4 --time 100ms

Firmware

The firmware files (FPGA bitstreams) for the ASIX SIGMA/SIGMA2 have been provided by the vendor under a license which allows redistribution, and are available from the sigrok-firmware repository. See Firmware for installation instructions.

Differences between SIGMA and SIGMA2

The hardware of SIGMA and SIGMA2 is almost identical, up to few exceptions:

  • Seven one-color LEDs were replaced with two two-color LEDs.
  • A button was added. It can be used to start, stop, trigger.
  • The SIGMA has input TTLs in DIL sockets, SIGMA2 is has input TTLs in SMD package.

The new hardware revision requires the new firmware files to support the button and the different LED wiring. The new firmware is usable for both SIGMA and SIGMA2. However, the new hardware revision cannot work with the old firmware files.

Resources

Retrieved from "https://sigrok.org/w/index.php?title=ASIX_SIGMA_/_SIGMA2&oldid=15073"