Difference between revisions of "Hantek 4032L/Info"

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== PCB testpoints ==
== Pinouts ==


=== JTAG ===
=== JP2 JTAG ===


TODO.
  XC6SLX16 JTAG port
 
  1 - GND
  2 - TMS
  3 - TDO
  4 - TDI
  5 - TCK
  6 - +3.3V


=== SPI FLASH ===
=== JP5 WRITE ===


TODO.
  MX25L4005 write protect disable
 
  1 - nWP
  2 - +3.3V
 
=== JP6 RST ===
 
  XC6SLX16 configuration reset
 
  1 - PROGRAM_B
  2 - GND
 
=== JP7 FLASH_SPI ===
 
  MX25L4005 ISP
 
  1 - +3.3V
  2 - CK
  3 - DIN
  4 - DOUT
  5 - nCS
  6 - GND
 
== Modding ==
 
In stock configuration both FX2LP and FPGA boots from their serial EEPROMs, but with a small hw patch it is possible to boot both parts from PC:
* lift U3 pin 5 to disable FX2LP EEPROM boot
* remove R102 and solder it between R102's left pad (this is FPGA's M1 pin) and C135's left pad (this is Vcc) to switch FPGA config mode to Slave Serial. FX2LP's PC5 is FPGA's PROGRAM_B, PC3 is DATA, PC1 is CLOCK, PC0 must be driven high (this is SPI FLASH nCS)

Revision as of 16:33, 22 May 2013

USB descriptors

 Device Descriptor:
   bcdUSB:             0x0200
   bDeviceClass:         0x00
   bDeviceSubClass:      0x00
   bDeviceProtocol:      0x00
   bMaxPacketSize0:      0x40 (64)
   idVendor:           0x04B5 (ROHM LSI Systems USA, LLC)
   idProduct:          0x4032
   bcdDevice:          0x0000
   iManufacturer:        0x01
       0x0409: "ODM   "
   iProduct:             0x02
       0x0409: "LA-4032"
   iSerialNumber:        0x00
   bNumConfigurations:   0x01
 
 Configuration Descriptor:
   wTotalLength:       0x0020
   bNumInterfaces:       0x01
   bConfigurationValue:  0x01
   iConfiguration:       0x00
   bmAttributes:         0xA0 (Bus Powered Remote Wakeup)
   MaxPower:             0xFA (500 Ma)
 
 Interface Descriptor:
   bInterfaceNumber:     0x00
   bAlternateSetting:    0x00
   bNumEndpoints:        0x02
   bInterfaceClass:      0xFF
   bInterfaceSubClass:   0x00
   bInterfaceProtocol:   0x00
   iInterface:           0x00

 Endpoint Descriptor:
   bEndpointAddress:     0x02
   Transfer Type:        Bulk
   wMaxPacketSize:     0x0200 (512)
   bInterval:            0x00
 
 Endpoint Descriptor:
   bEndpointAddress:     0x86
   Transfer Type:        Bulk
   wMaxPacketSize:     0x0200 (512)
   bInterval:            0x00

Pinouts

JP2 JTAG

 XC6SLX16 JTAG port
 
 1 - GND
 2 - TMS
 3 - TDO
 4 - TDI
 5 - TCK
 6 - +3.3V

JP5 WRITE

 MX25L4005 write protect disable
 
 1 - nWP
 2 - +3.3V

JP6 RST

 XC6SLX16 configuration reset
 
 1 - PROGRAM_B
 2 - GND

JP7 FLASH_SPI

 MX25L4005 ISP
 
 1 - +3.3V
 2 - CK
 3 - DIN
 4 - DOUT
 5 - nCS
 6 - GND

Modding

In stock configuration both FX2LP and FPGA boots from their serial EEPROMs, but with a small hw patch it is possible to boot both parts from PC:

  • lift U3 pin 5 to disable FX2LP EEPROM boot
  • remove R102 and solder it between R102's left pad (this is FPGA's M1 pin) and C135's left pad (this is Vcc) to switch FPGA config mode to Slave Serial. FX2LP's PC5 is FPGA's PROGRAM_B, PC3 is DATA, PC1 is CLOCK, PC0 must be driven high (this is SPI FLASH nCS)
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