Difference between revisions of "Main Page"
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File:Zeroplus Logic Cube.jpg|<small>'''[[Zeroplus Logic Cube]]'''<br />(planned)</small> | File:Zeroplus Logic Cube.jpg|<small>'''[[Zeroplus Logic Cube]]'''<br />(planned)</small> | ||
File:Buspirate v3.jpg|<small>'''[[Buspirate]]'''<br />(planned)</small> | File:Buspirate v3.jpg|<small>'''[[Buspirate]]'''<br />(planned)</small> | ||
File: | File:Intronix Logicport.jpg|<small>'''[[Intronix Logicport]]'''<br />(planned)</small> | ||
</gallery> | </gallery> | ||
Revision as of 16:27, 1 April 2010
The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source logic analyzer software that supports various (usually USB-based) logic analyzer hardware products. The code is licensed under the terms of the GNU GPL.
Design goals
- Hardware support. Supports a wide variety of logic analyzer hardware from various vendors with different capabilities.
- Cross-platform. Works on Linux, Mac OS X and Windows, and on architectures including x86, ARM, Sparc and PowerPC.
- Scriptable. Extendable with protocol decoders and analyzers written in Python.
- Format support. Supports various input and output formats (raw, CSV, gnuplot, VCD, others).
Supported hardware
Saleae Logic
(supported)- Open workbench logic sniffer.jpg
Openbench Logic Sniffer
(work in progress) CWAV USBee SX
(coming up)Braintechnology USB-LPS
(planned)Zeroplus Logic Cube
(planned)- Buspirate v3.jpg
Buspirate
(planned) Intronix Logicport
(planned)
Development
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Documentation |
Getting in touch
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IMPORTANT: Please note that (unless explicitly specified otherwise) all contents in this wiki (including text and images) are released to the CC-BY-SA 3.0. If you don't want that, please explicitly specify another free-ish license when adding pages or images to the wiki!