Difference between revisions of "Sysclk AX-Pro"

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{{Infobox logic analyzer
{{Infobox logic analyzer
| image            = [[File:SysCLK_AX_Pro_box.jpg|180px]]
| image            = [[File:Sysclk ax pro mugshot.png|180px]]
| name            = USBee AX Pro
| name            = Sysclk AX-Pro
| status          = in progress
| status          = supported
| source_code_dir  = fx2lafw
| source_code_dir  = fx2lafw
| channels        = 8
| channels        = 8 + 1
| analog channels  = 8
| samplerate      = 8ch @ 24MHz, 8+1ch @ 12MHz
| samplerate      = 24MHz
| samplerate_state = —
| samplerate_state = —
| triggers        = none (SW-only)
| triggers        = none (SW-only)
| voltages        = digital -1 to +6V<br/>
| voltages        = Digital: -1V &mdash; +6V<br/>Analog: ±10V (±20V max)
                    analog ±10V (±20 V max)
| threshold        = Fixed: V<sub>IH</sub>=1.6V, V<sub>IL</sub>=1.4V
| threshold        = Fixed: VIH=1.6V, VIL=1.4V
| memory          = none
| memory          = none
| compression      = none
| compression      = none
| website          = [http://sysclk.taobao.com/ SysCLK]
| price            = $35 - $45
| website          = [http://sysclk.taobao.com/ sysclk.taobao.com]
}}
}}


The '''SysCLK USBee AX Pro''' is a USB-based, 8-channel logic analyzer with up to 24MHz sampling rate, and with 2 additional analog channels multiplexed by relay to one ADC.
The '''Sysclk AX-Pro''' is a USB-based, 8-channel logic analyzer with up to 24MHz sampling rate, with 1 additional analog channel (theoretically 2, but only one of them can be used at a time; 3MHz analog bandwidth).


It is a clone of the [[CWAV USBee AX-Pro]].
It is a clone of the [[CWAV USBee AX-Pro]].
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In sigrok, we use the open-source [[fx2lafw]] firmware for this logic analyzer.
In sigrok, we use the open-source [[fx2lafw]] firmware for this logic analyzer.


'''Note''': Only the logic analyzer functionality is supported so far, analog support is work in progress.  
'''Note''': [[fx2lafw]] currently doesn't support switching between the two possible analog channels, ACH2 will be used unconditionally.


See [[SysCLK_AX-Pro/Info]] for some more details (such as '''lsusb -vvv''' output) on the device.
See [[Sysclk AX-Pro/Info]] for some more details (such as '''lsusb -v''' output) on the device.


== Hardware ==
== Hardware ==
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* '''Main chip''': [http://www.cypress.com/?docID=45142 Cypress CY7C68013A-56LTXC (FX2LP)]
* '''Main chip''': [http://www.cypress.com/?docID=45142 Cypress CY7C68013A-56LTXC (FX2LP)]
* '''I2C EEPROM''': [http://www.atmel.com/Images/doc0180.pdf‎ Atmel ATML125 24C02N SU27 D]
* '''I2C EEPROM''': [http://www.atmel.com/Images/doc0180.pdf‎ Atmel ATML125 24C02N SU27 D]
* '''Auxillary 8051 chip''': [http://www.stcmcu.com/datasheet/stc/STC-AD-PDF/STC15F204EA-series-english.pdf STC STC15F104E]. Functional is unknown for me
* '''Auxiliary 8051 chip''': [http://www.stcmcu.com/datasheet/stc/STC-AD-PDF/STC15F204EA-series-english.pdf STC STC15F104E] (purpose is unknown)
* '''Supply voltage regulator''': Advanced Monolithic Systems AMS1117-3.3
* '''Supply voltage regulator''': Advanced Monolithic Systems AMS1117-3.3
* '''Reference voltage regulator''': Advanced Monolithic Systems AMS1117-2.851218
* '''Reference voltage regulator''': Advanced Monolithic Systems AMS1117-2.851218
* '''Analog-to-Digital converter''': [http://www.ti.com/lit/ds/symlink/tlc5510.pdf Texas Instruments TLC5510I]
* '''Analog-to-Digital converter''': [http://www.ti.com/lit/ds/symlink/tlc5510.pdf Texas Instruments TLC5510I]
* '''Analog input amplifiers''': [http://www.analog.com/static/imported-files/data_sheets/AD8065_8066.pdf Analog Devices AD8065]
* '''Analog input amplifiers''': [http://www.analog.com/static/imported-files/data_sheets/AD8065_8066.pdf Analog Devices AD8065] (SMD marking "HRA")
* '''Analog amplifiers negative supply''': [http://www.ti.com/lit/ds/symlink/lmc7660.pdf Texas Instruments LMC7660]
* '''Analog amplifiers negative supply''': [http://www.ti.com/lit/ds/symlink/lmc7660.pdf Texas Instruments LMC7660]
* '''Some operational amplifiers''': [http://www.ti.com/lit/ds/symlink/lm158-n.pdf Texas Instruments LM358]
* '''Some operational amplifiers''': [http://www.ti.com/lit/ds/symlink/lm158-n.pdf Texas Instruments LM358]
* '''Analog channel switching relay''': TQ2-2V
* '''Analog channel switching relay''': TQ2-2V
* '''Crystal''': 24MHz
* '''Crystal''': 24MHz
* ...
 
The analog channels are multiplexed by relay or solid-state IC to one ADC.


=== FX2LP pin mappings ===
=== FX2LP pin mappings ===
{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
{| border="0" style="font-size: smaller;" class="alternategrey sigroktable"
|-  
|-  
! #      !! Pin          !! Destination !! Remark
! #      !! Pin          !! Destination !! Remark
|-
|-
| 01    || RDY0/SLRD    || TRIG        || input
| 01    || RDY0/SLRD    || TRIG        || socket pin
|-
|-
| 13    || IFCLK        || GND        || grounded
| 13    || IFCLK        || GND        || grounded
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| 18..25 || PB0..7      || DCH0..7    || digital input
| 18..25 || PB0..7      || DCH0..7    || digital input
|-
|-
| 30    || CTL1/FLAGB  || CLK        || socket
| 30    || CTL1/FLAGB  || CLK        || socket pin
|-
| 31    || CTL2/FLAGC  || ADC_CLK    || ADC clock input
|-
|-
| 33    || PA0          || relay      || multiplexing ACH1/ACH2
| 33    || PA0          || relay      || multiplexing ACH1/ACH2
|-
|-
| 35    || PA2          || GND1        || can be isolated from GND and act as aux socket io pin
| 35    || PA2          || DCH1 GND    || can be isolated from GND and act as aux socket pin
|-
|-
| 36    || PA3          || GND2        || can be isolated from GND and act as aux socket io pin
| 36    || PA3          || DCH2 GND    || can be isolated from GND and act as aux socket pin
|-
|-
| 38    || PA5          || STC#P3.1    || aux 8051 chip
| 38    || PA5          || STC_P3.1    || aux 8051 chip
|-
|-
| 39    || PA6          || STC#P3.3    || aux 8051 chip
| 39    || PA6          || STC_P3.3    || aux 8051 chip
|-
|-
| 42    || RESET#      || STC#P3.2    || aux 8051 chip
| 42    || RESET#      || STC_P3.2    || aux 8051 chip
|-
|-
| 44    || WAKEUP      || NC          || not connected
| 44    || WAKEUP      || NC          || not connected
|-
|-
| 45..52 || PD0..7      || ADC0..7    || ADC output
| 45..52 || PD0..7      || ADC_D1..8  || ADC data output
|}
|}


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<gallery>
<gallery>
File:SysCLK_AX_Pro_box.jpg|<small>AX-Pro</small>
File:SysCLK_AX_Pro_box.jpg|<small>Device, top</small>
File:SysCLK_AX_Pro_top.jpg|<small>PCB, top</small>
File:SysCLK_AX_Pro_top.jpg|<small>PCB, top</small>
File:SysCLK_AX_Pro_bottom.jpg|<small>PCB, bottom</small>
File:SysCLK_AX_Pro_bottom.jpg|<small>PCB, bottom</small>
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== Resources ==
== Resources ==


* [http://sysclk.taobao.com/ SysCLK Taobao shop] ([http://translate.google.com/translate?sl=zh-CN&tl=en&js=n&prev=_t&hl=en&ie=UTF-8&layout=2&eotf=1&u=http://sysclk.taobao.com/&act=url English translation])
* [http://sysclk.taobao.com/ Sysclk Taobao shop] ([http://translate.google.com/translate?sl=zh-CN&tl=en&js=n&prev=_t&hl=en&ie=UTF-8&layout=2&eotf=1&u=http://sysclk.taobao.com/&act=url English translation])


[[Category:Device]]
[[Category:Device]]

Latest revision as of 14:54, 30 June 2019

Sysclk AX-Pro
Sysclk ax pro mugshot.png
Status supported
Source code fx2lafw
Channels 8 + 1
Samplerate 8ch @ 24MHz, 8+1ch @ 12MHz
Samplerate (state) —
Triggers none (SW-only)
Min/max voltage Digital: -1V — +6V
Analog: ±10V (±20V max)
Threshold voltage Fixed: VIH=1.6V, VIL=1.4V
Memory none
Compression none
Price range $35 - $45
Website sysclk.taobao.com

The Sysclk AX-Pro is a USB-based, 8-channel logic analyzer with up to 24MHz sampling rate, with 1 additional analog channel (theoretically 2, but only one of them can be used at a time; 3MHz analog bandwidth).

It is a clone of the CWAV USBee AX-Pro.

In sigrok, we use the open-source fx2lafw firmware for this logic analyzer.

Note: fx2lafw currently doesn't support switching between the two possible analog channels, ACH2 will be used unconditionally.

See Sysclk AX-Pro/Info for some more details (such as lsusb -v output) on the device.

Hardware

The analog channels are multiplexed by relay or solid-state IC to one ADC.

FX2LP pin mappings

# Pin Destination Remark
01 RDY0/SLRD TRIG socket pin
13 IFCLK GND grounded
18..25 PB0..7 DCH0..7 digital input
30 CTL1/FLAGB CLK socket pin
31 CTL2/FLAGC ADC_CLK ADC clock input
33 PA0 relay multiplexing ACH1/ACH2
35 PA2 DCH1 GND can be isolated from GND and act as aux socket pin
36 PA3 DCH2 GND can be isolated from GND and act as aux socket pin
38 PA5 STC_P3.1 aux 8051 chip
39 PA6 STC_P3.3 aux 8051 chip
42 RESET# STC_P3.2 aux 8051 chip
44 WAKEUP NC not connected
45..52 PD0..7 ADC_D1..8 ADC data output

Photos

  • Device, top

  • PCB, top

  • PCB, bottom

Protocol

Since we use the open-source fx2lafw firmware for this device, we don't need to know the protocol.

Resources

Retrieved from "https://sigrok.org/w/index.php?title=Sysclk_AX-Pro&oldid=14402"