# Repeated START condition (Sr): same as S
# STOP condition (P): SDA = rising, SCL = high
#
-# All data bytes on SDA are extactly 8 bits long (transmitted MSB-first).
+# All data bytes on SDA are exactly 8 bits long (transmitted MSB-first).
# Each byte has to be followed by a 9th ACK/NACK bit. If that bit is low,
# that indicates an ACK, if it's high that indicates a NACK.
#
# After the first START condition, a master sends the device address of the
# slave it wants to talk to. Slave addresses are 7 bits long (MSB-first).
-# After those 7 bits a data direction bit is sent. If the bit is low that
+# After those 7 bits, a data direction bit is sent. If the bit is low that
# indicates a WRITE operation, if it's high that indicates a READ operation.
#
# Later an optional 10bit slave addressing scheme was added.
# TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
# TODO: Implement support for detecting various bus errors.
-# TODO: Return two buffers, one with structured data for the GUI to parse
-# and display, and one with human-readable ASCII output.
+#
+# I2C output format:
+#
+# The output consists of a (Python) list of I2C "packets", each of which
+# has an (implicit) index number (its index in the list).
+# Each packet consists of a Python dict with certain key/value pairs.
+#
+# TODO: Make this a list later instead of a dict?
+#
+# 'type': (string)
+# - 'S' (START condition)
+# - 'Sr' (Repeated START)
+# - 'AR' (Address, read)
+# - 'AW' (Address, write)
+# - 'DR' (Data, read)
+# - 'DW' (Data, write)
+# - 'P' (STOP condition)
+# 'range': (tuple of 2 integers, the min/max samplenumber of this range)
+# - (min, max)
+# - min/max can also be identical.
+# 'data': (actual data as integer ???) TODO: This can be very variable...
+# 'ann': (string; additional annotations / comments)
+#
+# Example output:
+# [{'type': 'S', 'range': (150, 160), 'data': None, 'ann': 'Foobar'},
+# {'type': 'AW', 'range': (200, 300), 'data': 0x50, 'ann': 'Slave 4'},
+# {'type': 'DW', 'range': (310, 370), 'data': 0x00, 'ann': 'Init cmd'},
+# {'type': 'AR', 'range': (500, 560), 'data': 0x50, 'ann': 'Get stat'},
+# {'type': 'DR', 'range': (580, 640), 'data': 0xfe, 'ann': 'OK'},
+# {'type': 'P', 'range': (650, 660), 'data': None, 'ann': None}]
+#
+# Possible other events:
+# - Error event in case protocol looks broken:
+# [{'type': 'ERROR', 'range': (min, max),
+# 'data': TODO, 'ann': 'This is not a Microchip 24XX64 EEPROM'},
+# [{'type': 'ERROR', 'range': (min, max),
+# 'data': TODO, 'ann': 'TODO'},
+# - TODO: Make list of possible errors accessible as metadata?
+#
+# TODO: I2C address of slaves.
+# TODO: Handle multiple different I2C devices on same bus
+# -> we need to decode multiple protocols at the same time.
+# TODO: range: Always contiguous? Splitted ranges? Multiple per event?
+#
+
+#
+# I2C input format:
+#
+# signals:
+# [[id, channel, description], ...] # TODO
+#
+# Example:
+# {'id': 'SCL', 'ch': 5, 'desc': 'Serial clock line'}
+# {'id': 'SDA', 'ch': 7, 'desc': 'Serial data line'}
+# ...
+#
+# {'inbuf': [...],
+# 'signals': [{'SCL': }]}
+#
-def sigrokdecode_i2c(inbuf):
+def decode(inbuf):
"""I2C protocol decoder"""
+ # FIXME: Get the data in the correct format in the first place.
+ inbuf = [ord(x) for x in inbuf]
+
# FIXME: This should be passed in as metadata, not hardcoded here.
- signals = (2, 5)
- channels = 8
+ metadata = {
+ 'numchannels': 8,
+ 'signals': {
+ 'scl': {'ch': 5, 'name': 'SCL', 'desc': 'Serial clock line'},
+ 'sda': {'ch': 7, 'name': 'SDA', 'desc': 'Serial data line'},
+ },
+ }
- o = wr = ack = d = ''
+ out = []
+ o = ack = d = ''
bitcount = data = 0
- state = 'IDLE'
+ wr = startsample = -1
+ IDLE, START, ADDRESS, DATA = range(4)
+ state = IDLE
- # Get the bit number (and thus probe index) of the SCL/SDA signals.
- scl_bit, sda_bit = signals
+ # Get the channel/probe number of the SCL/SDA signals.
+ scl_bit = metadata['signals']['scl']['ch']
+ sda_bit = metadata['signals']['sda']['ch']
# Get SCL/SDA bit values (0/1 for low/high) of the first sample.
- s = ord(inbuf[0])
- oldscl = (s & (1 << scl_bit)) != 0
- oldsda = (s & (1 << sda_bit)) != 0
+ s = inbuf[0]
+ oldscl = (s & (1 << scl_bit)) >> scl_bit
+ oldsda = (s & (1 << sda_bit)) >> sda_bit
# Loop over all samples.
# TODO: Handle LAs with more/less than 8 channels.
for samplenum, s in enumerate(inbuf[1:]): # We skip the first byte...
-
- s = ord(s) # FIXME
-
# Get SCL/SDA bit values (0/1 for low/high).
- scl = (s & (1 << scl_bit)) != 0
- sda = (s & (1 << sda_bit)) != 0
+ scl = (s & (1 << scl_bit)) >> scl_bit
+ sda = (s & (1 << sda_bit)) >> sda_bit
# TODO: Wait until the bus is idle (SDA = SCL = 1) first?
# START condition (S): SDA = falling, SCL = high
if (oldsda == 1 and sda == 0) and scl == 1:
- o += "%d\t\tSTART\n" % samplenum
- state = 'ADDRESS'
+ o = {'type': 'S', 'range': (samplenum, samplenum),
+ 'data': None, 'ann': None},
+ out.append(o)
+ state = ADDRESS
bitcount = data = 0
# Data latching by transmitter: SCL = low
# Data sampling of receiver: SCL = rising
elif (oldscl == 0 and scl == 1):
+ if startsample == -1:
+ startsample = samplenum
bitcount += 1
- # o += "%d\t\tRECEIVED BIT %d: %d\n" % \
- # (samplenum, 8 - bitcount, sda)
+ # out.append("%d\t\tRECEIVED BIT %d: %d\n" % \
+ # (samplenum, 8 - bitcount, sda))
# Address and data are transmitted MSB-first.
data <<= 1
# We received 8 address/data bits and the ACK/NACK bit.
data >>= 1 # Shift out unwanted ACK/NACK bit here.
- o += "%d\t\t%s: " % (samplenum, state)
- ack = (sda == 1) and 'NACK' or 'ACK'
- d = (state == 'ADDRESS') and (data & 0xfe) or data
- wr = ''
- if state == 'ADDRESS':
- wr = (data & 1) and ' (W)' or ' (R)'
- state = 'DATA'
- o += "0x%02x%s (%s)\n" % (d, wr, ack)
- bitcount = data = 0
+ ack = (sda == 1) and 'N' or 'A'
+ d = (state == ADDRESS) and (data & 0xfe) or data
+ if state == ADDRESS:
+ wr = (data & 1) and 1 or 0
+ state = DATA
+ o = {'type': state,
+ 'range': (startsample, samplenum - 1),
+ 'data': d, 'ann': None}
+ if state == ADDRESS and wr == 1:
+ o['type'] = 'AW'
+ elif state == ADDRESS and wr == 0:
+ o['type'] = 'AR'
+ elif state == DATA and wr == 1:
+ o['type'] = 'DW'
+ elif state == DATA and wr == 0:
+ o['type'] = 'DR'
+ out.append(o)
+ o = {'type': ack, 'range': (samplenum, samplenum),
+ 'data': None, 'ann': None}
+ out.append(o)
+ bitcount = data = startsample = 0
+ startsample = -1
# STOP condition (P): SDA = rising, SCL = high
elif (oldsda == 0 and sda == 1) and scl == 1:
- o += "%d\t\tSTOP\n" % samplenum
- state = 'IDLE'
+ o = {'type': 'P', 'range': (samplenum, samplenum),
+ 'data': None, 'ann': None},
+ out.append(o)
+ state = IDLE
+ wr = -1
# Save current SDA/SCL values for the next round.
oldscl = scl
oldsda = sda
- return o
+ # FIXME: Just for testing...
+ return str(out)
-# This is just a draft.
-def sigrokdecode_register_i2c():
- metadata = {
+def register():
+ return {
'id': 'i2c',
'name': 'I2C',
- 'description': 'Inter-Integrated Circuit (I2C) bus',
- 'function': 'sigrokdecode_i2c',
+ 'desc': 'Inter-Integrated Circuit (I2C) bus',
'inputformats': ['raw'],
'signalnames': {
'SCL': 'Serial clock line',
'SDA': 'Serial data line',
},
- 'ouputformats': ['i2c', 'ascii'],
+ 'outputformats': ['i2c'],
}
- return metadata
# Use psyco (if available) as it results in huge performance improvements.
try:
import psyco
- psyco.bind(sigrokdecode_i2c)
+ psyco.bind(decode)
except ImportError:
pass
projects / libsigrokdecode.git / blobdiff