decoders: Rephrase condition-less .wait() calls (self documentation)

[libsigrokdecode.git] / decoders / z80 / pd.py

diff --git a/decoders/z80/pd.py b/decoders/z80/pd.py
index f6bafb11f9ad2901db8f5df9fec19d0a33228a8e..76e1858ff98b6e1748499180915a206bc80a1caa 100644 (file)
--- a/decoders/z80/pd.py
+++ b/decoders/z80/pd.py
@@ -56,7 +56,7 @@ ann_data_cycle_map = {
 
 def reduce_bus(bus):
     if 0xFF in bus:
-        return None # unassigned bus probes
+        return None # unassigned bus channels
     else:
         return reduce(lambda a, b: (a << 1) | b, reversed(bus))
 
@@ -64,7 +64,7 @@ def signed_byte(byte):
     return byte if byte < 128 else byte - 256
 
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 3
     id       = 'z80'
     name     = 'Z80'
     longname = 'Zilog Z80 CPU'
@@ -72,7 +72,7 @@ class Decoder(srd.Decoder):
     license  = 'gplv3+'
     inputs   = ['logic']
     outputs  = ['z80']
-    probes = tuple({
+    channels = tuple({
             'id': 'd%d' % i,
             'name': 'D%d' % i,
             'desc': 'Data bus line %d' % i
@@ -82,7 +82,7 @@ class Decoder(srd.Decoder):
         {'id': 'rd', 'name': '/RD', 'desc': 'Memory or I/O read'},
         {'id': 'wr', 'name': '/WR', 'desc': 'Memory or I/O write'},
     )
-    optional_probes = (
+    optional_channels = (
         {'id': 'mreq', 'name': '/MREQ', 'desc': 'Memory request'},
         {'id': 'iorq', 'name': '/IORQ', 'desc': 'I/O request'},
     ) + tuple({
@@ -110,7 +110,7 @@ class Decoder(srd.Decoder):
         ('warnings', 'Warnings', (Ann.WARN,))
     )
 
-    def __init__(self, **kwargs):
+    def __init__(self):
         self.prev_cycle = Cycle.NONE
         self.op_state   = self.state_IDLE
 
@@ -129,8 +129,10 @@ class Decoder(srd.Decoder):
         self.op_state   = self.state_IDLE
         self.instr_len  = 0
 
-    def decode(self, ss, es, data):
-        for (self.samplenum, pins) in data:
+    def decode(self):
+        while True:
+            # TODO: Come up with more appropriate self.wait() conditions.
+            pins = self.wait()
             cycle = Cycle.NONE
             if pins[Pin.MREQ] != 1: # default to asserted
                 if pins[Pin.RD] == 0: