- 'BIT', <bit>
- 'STUFF BIT', None
- 'EOP', None
+ - 'ERR', None
<sym>:
- 'J', 'K', 'SE0', or 'SE1'
<bit>:
- - 0 or 1
+ - '0' or '1'
- Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'.
'''
'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
}
-sym_idx = {
- 'J': 0,
- 'K': 1,
- 'SE0': 2,
- 'SE1': 3,
+sym_annotation = {
+ 'J': [0, ['J']],
+ 'K': [1, ['K']],
+ 'SE0': [2, ['SE0', '0']],
+ 'SE1': [3, ['SE1', '1']],
}
class SamplerateError(Exception):
('eop', 'End of packet (EOP)'),
('bit', 'Bit'),
('stuffbit', 'Stuff bit'),
+ ('error', 'Error'),
)
annotation_rows = (
- ('bits', 'Bits', (4, 5, 6, 7)),
+ ('bits', 'Bits', (4, 5, 6, 7, 8)),
('symbols', 'Symbols', (0, 1, 2, 3)),
)
def __init__(self):
self.samplerate = None
self.oldsym = 'J' # The "idle" state is J.
- self.ss_sop = None
self.ss_block = None
self.samplenum = 0
self.syms = []
if sym != 'K':
self.oldsym = sym
return
- self.ss_sop = self.samplenum
- self.samplepos = self.ss_sop - (self.bitwidth / 2) + 0.5
+ self.consecutive_ones = 0
+ self.samplepos = self.samplenum - (self.bitwidth / 2) + 0.5
self.set_new_target_samplenum()
self.putpx(['SOP', None])
self.putx([4, ['SOP', 'S']])
self.state = 'GET BIT'
def handle_bit(self, sym, b):
- if self.consecutive_ones == 6 and b == '0':
- # Stuff bit.
- self.putpb(['STUFF BIT', None])
- self.putb([7, ['Stuff bit: %s' % b, 'SB: %s' % b, '%s' % b]])
- self.putb([sym_idx[sym], ['%s' % sym]])
- self.consecutive_ones = 0
+ if self.consecutive_ones == 6:
+ if b == '0':
+ # Stuff bit.
+ self.putpb(['STUFF BIT', None])
+ self.putb([7, ['Stuff bit: 0', 'SB: 0', '0']])
+ self.consecutive_ones = 0
+ else:
+ self.putpb(['ERR', None])
+ self.putb([8, ['Bit stuff error', 'BS ERR', 'B']])
+ self.state = 'IDLE'
else:
# Normal bit (not a stuff bit).
self.putpb(['BIT', b])
self.putb([6, ['%s' % b]])
- self.putb([sym_idx[sym], ['%s' % sym]])
if b == '1':
self.consecutive_ones += 1
else:
# EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
self.syms.append(sym)
self.putpb(['SYM', sym])
- self.putb([sym_idx[sym], ['%s' % sym, '%s' % sym[0]]])
+ self.putb(sym_annotation[sym])
self.set_new_target_samplenum()
self.oldsym = sym
if self.syms[-2:] == ['SE0', 'J']:
self.putpm(['EOP', None])
self.putm([5, ['EOP', 'E']])
self.syms, self.state = [], 'IDLE'
- self.consecutive_ones = 0
self.bitwidth = float(self.samplerate) / float(self.bitrate)
def get_bit(self, sym):
self.syms.append(sym)
self.putpb(['SYM', sym])
b = '0' if self.oldsym != sym else '1'
+ self.putb(sym_annotation[sym])
if self.oldsym != sym:
edgesym = symbols[self.options['signalling']][tuple(self.edgepins)]
if edgesym not in ('SE0', 'SE1'):