usb_signalling: decode RESET and Keep-Alive signalling conditions

[libsigrokdecode.git] / decoders / usb_signalling / pd.py

diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py
index 774ed494f839105c1ea6b8068849bc92a0578f86..e0fd2916acbf0cab5166c6caacdf18664abeeb88 100644 (file)
--- a/decoders/usb_signalling/pd.py
+++ b/decoders/usb_signalling/pd.py
@@ -34,6 +34,8 @@ Packet:
  - 'STUFF BIT', None
  - 'EOP', None
  - 'ERR', None
+ - 'KEEP ALIVE', None
+ - 'RESET', None
 
 <sym>:
  - 'J', 'K', 'SE0', or 'SE1'
@@ -104,9 +106,11 @@ class Decoder(srd.Decoder):
         ('bit', 'Bit'),
         ('stuffbit', 'Stuff bit'),
         ('error', 'Error'),
+        ('keep-alive', 'Low-speed keep-alive'),
+        ('reset', 'Reset'),
     )
     annotation_rows = (
-        ('bits', 'Bits', (4, 5, 6, 7, 8)),
+        ('bits', 'Bits', (4, 5, 6, 7, 8, 9, 10)),
         ('symbols', 'Symbols', (0, 1, 2, 3)),
     )
 
@@ -120,10 +124,11 @@ class Decoder(srd.Decoder):
         self.samplepos = None
         self.samplenum_target = None
         self.samplenum_edge = None
+        self.samplenum_lastedge = 0
         self.oldpins = None
         self.edgepins = None
         self.consecutive_ones = 0
-        self.state = 'IDLE'
+        self.state = 'INIT'
 
     def start(self):
         self.out_python = self.register(srd.OUTPUT_PYTHON)
@@ -134,39 +139,40 @@ class Decoder(srd.Decoder):
             self.samplerate = value
             self.bitrate = bitrates[self.options['signalling']]
             self.bitwidth = float(self.samplerate) / float(self.bitrate)
-            self.halfbit = int(self.bitwidth / 2)
 
     def putpx(self, data):
-        self.put(self.samplenum, self.samplenum, self.out_python, data)
+        s = self.samplenum_edge
+        self.put(s, s, self.out_python, data)
 
     def putx(self, data):
-        self.put(self.samplenum, self.samplenum, self.out_ann, data)
+        s = self.samplenum_edge
+        self.put(s, s, self.out_ann, data)
 
     def putpm(self, data):
-        s, h = self.samplenum, self.halfbit
-        self.put(self.ss_block - h, s + h, self.out_python, data)
+        e = self.samplenum_edge
+        self.put(self.ss_block, e, self.out_python, data)
 
     def putm(self, data):
-        s, h = self.samplenum, self.halfbit
-        self.put(self.ss_block - h, s + h, self.out_ann, data)
+        e = self.samplenum_edge
+        self.put(self.ss_block, e, self.out_ann, data)
 
     def putpb(self, data):
-        s, h = self.samplenum, self.halfbit
-        self.put(self.samplenum_edge, s + h, self.out_python, data)
+        s, e = self.samplenum_lastedge, self.samplenum_edge
+        self.put(s, e, self.out_python, data)
 
     def putb(self, data):
-        s, h = self.samplenum, self.halfbit
-        self.put(self.samplenum_edge, s + h, self.out_ann, data)
+        s, e = self.samplenum_lastedge, self.samplenum_edge
+        self.put(s, e, self.out_ann, data)
 
     def set_new_target_samplenum(self):
         self.samplepos += self.bitwidth;
         self.samplenum_target = int(self.samplepos)
+        self.samplenum_lastedge = self.samplenum_edge
         self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2))
 
     def wait_for_sop(self, sym):
         # Wait for a Start of Packet (SOP), i.e. a J->K symbol change.
-        if sym != 'K':
-            self.oldsym = sym
+        if sym != 'K' or self.oldsym != 'J':
             return
         self.consecutive_ones = 0
         self.samplepos = self.samplenum - (self.bitwidth / 2) + 0.5
@@ -197,9 +203,9 @@ class Decoder(srd.Decoder):
 
     def get_eop(self, sym):
         # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
+        self.set_new_target_samplenum()
         self.putpb(['SYM', sym])
         self.putb(sym_annotation[sym])
-        self.set_new_target_samplenum()
         self.oldsym = sym
         if sym == 'SE0':
             pass
@@ -215,10 +221,11 @@ class Decoder(srd.Decoder):
             self.state = 'IDLE'
 
     def get_bit(self, sym):
+        self.set_new_target_samplenum()
         if sym == 'SE0':
             # Start of an EOP. Change state, save edge
             self.state = 'GET EOP'
-            self.ss_block = self.samplenum
+            self.ss_block = self.samplenum_lastedge
         else:
             b = '0' if self.oldsym != sym else '1'
             self.handle_bit(b)
@@ -233,9 +240,19 @@ class Decoder(srd.Decoder):
                 else:
                     self.bitwidth = self.bitwidth + (0.001 * self.bitwidth)
                     self.samplepos = self.samplepos + (0.01 * self.bitwidth)
-        self.set_new_target_samplenum()
         self.oldsym = sym
 
+    def handle_idle(self, sym):
+        self.samplenum_edge = self.samplenum
+        se0_length = float(self.samplenum - self.samplenum_lastedge) / self.samplerate
+        if se0_length > 2.5e-6: # 2.5us
+            self.putpb(['RESET', None])
+            self.putb([10, ['Reset', 'Res', 'R']])
+        elif se0_length > 1.2e-6 and self.options['signalling'] == 'low-speed':
+            self.putpb(['KEEP ALIVE', None])
+            self.putb([9, ['Keep-alive', 'KA', 'A']])
+        self.state = 'IDLE'
+
     def decode(self, ss, es, data):
         if not self.samplerate:
             raise SamplerateError('Cannot decode without samplerate.')
@@ -247,7 +264,11 @@ class Decoder(srd.Decoder):
                     continue
                 self.oldpins = pins
                 sym = symbols[self.options['signalling']][tuple(pins)]
-                self.wait_for_sop(sym)
+                if sym == 'SE0':
+                    self.samplenum_lastedge = self.samplenum
+                    self.state = 'WAIT IDLE'
+                else:
+                    self.wait_for_sop(sym)
                 self.edgepins = pins
             elif self.state in ('GET BIT', 'GET EOP'):
                 # Wait until we're in the middle of the desired bit.
@@ -260,3 +281,17 @@ class Decoder(srd.Decoder):
                     self.get_bit(sym)
                 elif self.state == 'GET EOP':
                     self.get_eop(sym)
+            elif self.state == 'WAIT IDLE':
+                if self.oldpins == pins:
+                    continue
+                sym = symbols[self.options['signalling']][tuple(pins)]
+                if self.samplenum - self.samplenum_lastedge > 1:
+                    self.handle_idle(sym)
+                else:
+                    self.wait_for_sop(sym)
+                self.oldpins = pins
+                self.edgepins = pins
+            elif self.state == 'INIT':
+                sym = symbols[self.options['signalling']][tuple(pins)]
+                self.handle_idle(sym)
+                self.oldpins = pins