## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
##
import sigrokdecode as srd
(0, 1): 'LS_J',
(1, 1): 'SE1',
},
+ # After a PREamble PID, the bus segment between Host and Hub uses LS
+ # signalling rate and FS signalling polarity (USB 2.0 spec, 11.8.4: "For
+ # both upstream and downstream low-speed data, the hub is responsible for
+ # inverting the polarity of the data before transmitting to/from a
+ # low-speed port.").
+ 'low-speed-rp': {
+ # (<dp>, <dm>): <symbol/state>
+ (0, 0): 'SE0',
+ (1, 0): 'J',
+ (0, 1): 'K',
+ (1, 1): 'SE1',
+ },
}
bitrates = {
- 'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
+ 'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
+ 'low-speed-rp': 1500000, # 1.5Mb/s (+/- 1.5%)
'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
'automatic': None
}
pass
class Decoder(srd.Decoder):
- api_version = 2
+ api_version = 3
id = 'usb_signalling'
name = 'USB signalling'
longname = 'Universal Serial Bus (LS/FS) signalling'
- desc = 'USB (low-speed and full-speed) signalling protocol.'
+ desc = 'USB (low-speed/full-speed) signalling protocol.'
license = 'gplv2+'
inputs = ['logic']
outputs = ['usb_signalling']
+ tags = ['PC']
channels = (
{'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
{'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
)
def __init__(self):
+ self.reset()
+
+ def reset(self):
self.samplerate = None
self.oldsym = 'J' # The "idle" state is J.
self.ss_block = None
- self.samplenum = 0
self.bitrate = None
self.bitwidth = None
self.samplepos = None
self.samplenum_target = None
self.samplenum_edge = None
self.samplenum_lastedge = 0
- self.oldpins = None
self.edgepins = None
self.consecutive_ones = 0
- self.state = 'INIT'
+ self.bits = None
+ self.state = 'IDLE'
def start(self):
self.out_python = self.register(srd.OUTPUT_PYTHON)
self.put(s, e, self.out_ann, data)
def set_new_target_samplenum(self):
- self.samplepos += self.bitwidth;
+ self.samplepos += self.bitwidth
self.samplenum_target = int(self.samplepos)
self.samplenum_lastedge = self.samplenum_edge
self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2))
if sym != 'K' or self.oldsym != 'J':
return
self.consecutive_ones = 0
+ self.bits = ''
self.update_bitrate()
self.samplepos = self.samplenum - (self.bitwidth / 2) + 0.5
self.set_new_target_samplenum()
# Got an EOP.
self.putpm(['EOP', None])
self.putm([5, ['EOP', 'E']])
- self.state = 'IDLE'
+ self.state = 'WAIT IDLE'
else:
self.putpm(['ERR', None])
self.putm([8, ['EOP Error', 'EErr', 'E']])
def get_bit(self, sym):
self.set_new_target_samplenum()
+ b = '0' if self.oldsym != sym else '1'
+ self.oldsym = sym
if sym == 'SE0':
# Start of an EOP. Change state, save edge
self.state = 'GET EOP'
self.ss_block = self.samplenum_lastedge
else:
- b = '0' if self.oldsym != sym else '1'
self.handle_bit(b)
self.putpb(['SYM', sym])
self.putb(sym_annotation[sym])
- if self.oldsym != sym:
+ if len(self.bits) <= 16:
+ self.bits += b
+ if len(self.bits) == 16 and self.bits == '0000000100111100':
+ # Sync and low-speed PREamble seen
+ self.putpx(['EOP', None])
+ self.state = 'IDLE'
+ self.signalling = 'low-speed-rp'
+ self.update_bitrate()
+ self.oldsym = 'J'
+ if b == '0':
edgesym = symbols[self.signalling][tuple(self.edgepins)]
if edgesym not in ('SE0', 'SE1'):
if edgesym == sym:
else:
self.bitwidth = self.bitwidth + (0.001 * self.bitwidth)
self.samplepos = self.samplepos + (0.01 * self.bitwidth)
- self.oldsym = sym
def handle_idle(self, sym):
self.samplenum_edge = self.samplenum
elif sym == 'LS_J':
self.signalling = 'low-speed'
self.update_bitrate()
+ self.oldsym = 'J'
self.state = 'IDLE'
- def decode(self, ss, es, data):
+ def decode(self):
if not self.samplerate:
raise SamplerateError('Cannot decode without samplerate.')
- for (self.samplenum, pins) in data:
+
+ # Seed internal state from the very first sample.
+ pins = self.wait()
+ sym = symbols[self.options['signalling']][pins]
+ self.handle_idle(sym)
+
+ while True:
# State machine.
if self.state == 'IDLE':
- # Ignore identical samples early on (for performance reasons).
- if self.oldpins == pins:
- continue
- self.oldpins = pins
- sym = symbols[self.signalling][tuple(pins)]
+ # Wait for any edge on either DP and/or DM.
+ pins = self.wait([{0: 'e'}, {1: 'e'}])
+ sym = symbols[self.signalling][pins]
if sym == 'SE0':
self.samplenum_lastedge = self.samplenum
self.state = 'WAIT IDLE'
self.edgepins = pins
elif self.state in ('GET BIT', 'GET EOP'):
# Wait until we're in the middle of the desired bit.
- if self.samplenum == self.samplenum_edge:
- self.edgepins = pins
- if self.samplenum < self.samplenum_target:
- continue
- sym = symbols[self.signalling][tuple(pins)]
+ self.edgepins = self.wait([{'skip': self.samplenum_edge - self.samplenum}])
+ pins = self.wait([{'skip': self.samplenum_target - self.samplenum}])
+
+ sym = symbols[self.signalling][pins]
if self.state == 'GET BIT':
self.get_bit(sym)
elif self.state == 'GET EOP':
self.get_eop(sym)
elif self.state == 'WAIT IDLE':
- if self.oldpins == pins:
- continue
+ # Skip "all-low" input. Wait for high level on either DP or DM.
+ pins = self.wait()
+ while not pins[0] and not pins[1]:
+ pins = self.wait([{0: 'h'}, {1: 'h'}])
if self.samplenum - self.samplenum_lastedge > 1:
- sym = symbols[self.options['signalling']][tuple(pins)]
+ sym = symbols[self.options['signalling']][pins]
self.handle_idle(sym)
else:
- sym = symbols[self.signalling][tuple(pins)]
+ sym = symbols[self.signalling][pins]
self.wait_for_sop(sym)
- self.oldpins = pins
self.edgepins = pins
- elif self.state == 'INIT':
- sym = symbols[self.options['signalling']][tuple(pins)]
- self.handle_idle(sym)
- self.oldpins = pins
projects / libsigrokdecode.git / blobdiff