srd: extra module path can now optionally be passed to srd_init()

[libsigrokdecode.git] / decoders / usb / usb.py

diff --git a/decoders/usb/usb.py b/decoders/usb/usb.py
index 073fe0114d2824116ec6ff25fb5af60fd6c3aa99..99dd4b5addba0225441bbe84207a4ffe2cd83bdf 100644 (file)
--- a/decoders/usb/usb.py
+++ b/decoders/usb/usb.py
@@ -18,27 +18,7 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-#
-# USB Full-speed protocol decoder
-#
-# Full-speed USB signalling consists of two signal lines, both driven at 3.3V
-# logic levels. The signals are DP (D+) and DM (D-), and normally operate in
-# differential mode.
-# The state where DP=1,DM=0 is J, the state DP=0,DM=1 is K.
-# A state SE0 is defined where DP=DM=0. This common mode signal is used to
-# signal a reset or end of packet.
-#
-# Data transmitted on the USB is encoded with NRZI. A transition from J to K
-# or vice-versa indicates a logic 0, while no transition indicates a logic 1.
-# If 6 ones are transmitted consecutively, a zero is inserted to force a
-# transition. This is known as bit stuffing. Data is transferred at a rate
-# of 12Mbit/s. The SE0 transmitted to signal an end-of-packet is two bit
-# intervals long.
-#
-# Details:
-# https://en.wikipedia.org/wiki/USB
-# http://www.usb.org/developers/docs/
-#
+# USB (full-speed) protocol decoder
 
 import sigrokdecode as srd
 
@@ -105,6 +85,7 @@ def packet_decode(packet):
     return pid + ' ' + data
 
 class Decoder(srd.Decoder):
+    api_version = 1
     id = 'usb'
     name = 'USB'
     longname = 'Universal Serial Bus'
@@ -117,6 +98,7 @@ class Decoder(srd.Decoder):
         {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
         {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
     ]
+    optional_probes = []
     options = {}
     annotations = [
         ['TODO', 'TODO']
@@ -132,17 +114,18 @@ class Decoder(srd.Decoder):
         self.out_ann = self.add(srd.OUTPUT_ANN, 'usb')
 
         if self.rate < 48000000:
-            raise Exception('Sample rate not sufficient for USB decoding')
+            raise Exception('Sample rate (%d) not sufficient for USB '
+                            'decoding, need at least 48MHz' % self.rate)
 
         # Initialise decoder state.
         self.sym = J
         self.scount = 0
         self.packet = ''
 
-    def decode(self, ss, es, data):
+    def report(self):
+        pass
 
-        # FIXME
-        # for (samplenum, (dp, dm, x, y, z, a)) in data:
+    def decode(self, ss, es, data):
         for (samplenum, (dm, dp)) in data:
 
             self.scount += 1