srd: All PDs: Various fixes, cosmetics.

[libsigrokdecode.git] / decoders / uart / uart.py

diff --git a/decoders/uart/uart.py b/decoders/uart/uart.py
index f827a22d8a3d26b999e76f70b2c82f5906f0337b..a0f915cc2da2183f291fdbd11f7928a02b5906f0 100644 (file)
--- a/decoders/uart/uart.py
+++ b/decoders/uart/uart.py
@@ -199,6 +199,7 @@ class Decoder(srd.Decoder):
         {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
         {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
     ]
+    extra_probes = []
     options = {
         'baudrate': ['Baud rate', 115200],
         'num_data_bits': ['Data bits', 8], # Valid: 5-9.
@@ -391,7 +392,8 @@ class Decoder(srd.Decoder):
         self.put(self.samplenum, self.samplenum, self.out_ann,
                  [ANN_ASCII, ['Stop bit', 'Stop', 'P']])
 
-    def decode(self, ss, es, data): # TODO
+    def decode(self, ss, es, data):
+        # TODO: Either RX or TX could be omitted (optional probe).
         for (samplenum, (rx, tx)) in data:
 
             # TODO: Start counting at 0 or 1? Increase before or after?
@@ -420,7 +422,7 @@ class Decoder(srd.Decoder):
                 elif self.state[rxtx] == GET_STOP_BITS:
                     self.get_stop_bits(rxtx, signal)
                 else:
-                    raise Exception('Invalid state: %s' % self.state[rxtx])
+                    raise Exception('Invalid state: %d' % self.state[rxtx])
 
                 # Save current RX/TX values for the next round.
                 self.oldbit[rxtx] = signal