srd: Performance improvements for various PDs.

[libsigrokdecode.git] / decoders / uart / uart.py

diff --git a/decoders/uart/uart.py b/decoders/uart/uart.py
index 057a8900811f94503895c36247d5e66a9639455e..92c105ca0c0ff380f7e3c7a363063d2f75432069 100644 (file)
--- a/decoders/uart/uart.py
+++ b/decoders/uart/uart.py
@@ -61,8 +61,7 @@ class Decoder(srd.Decoder):
     id = 'uart'
     name = 'UART'
     longname = 'Universal Asynchronous Receiver/Transmitter'
-    desc = 'Universal Asynchronous Receiver/Transmitter (UART)'
-    longdesc = 'TODO.'
+    desc = 'Asynchronous, serial bus.'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['uart']
@@ -104,6 +103,7 @@ class Decoder(srd.Decoder):
         self.startsample = [-1, -1]
         self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
         self.oldbit = [None, None]
+        self.oldpins = None
 
     def start(self, metadata):
         self.samplerate = metadata['samplerate']
@@ -266,10 +266,12 @@ class Decoder(srd.Decoder):
 
     def decode(self, ss, es, data):
         # TODO: Either RX or TX could be omitted (optional probe).
-        for (samplenum, (rx, tx)) in data:
+        for (self.samplenum, pins) in data:
 
-            # TODO: Start counting at 0 or 1? Increase before or after?
-            self.samplenum += 1
+            # Ignore identical samples early on (for performance reasons).
+            if self.oldpins == pins:
+                continue
+            self.oldpins, (rx, tx) = pins, pins
 
             # First sample: Save RX/TX value.
             if self.oldbit[RX] == None: