All PDs: More consistent OUTPUT_PYTHON format docs.

[libsigrokdecode.git] / decoders / uart / pd.py

diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index f01cacece3e86b18274432a0ba1e4d87a7b0e4f2..ae99874c8f48762cfb10396d22e96bc03dcf09d4 100644 (file)
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -23,10 +23,10 @@ import sigrokdecode as srd
 '''
 OUTPUT_PYTHON format:
 
-UART packet:
-[<packet-type>, <rxtx>, <packet-data>]
+Packet:
+[<ptype>, <rxtx>, <pdata>]
 
-This is the list of <packet-type>s and their respective <packet-data>:
+This is the list of <ptype>s and their respective <pdata> values:
  - 'STARTBIT': The data is the (integer) value of the start bit (0/1).
  - 'DATA': The data is the (integer) value of the UART data. Valid values
    range from 0 to 512 (as the data can be up to 9 bits in size).
@@ -70,7 +70,7 @@ def parity_ok(parity_type, parity_bit, data, num_data_bits):
         raise Exception('Invalid parity type: %d' % parity_type)
 
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 2
     id = 'uart'
     name = 'UART'
     longname = 'Universal Asynchronous Receiver/Transmitter'
@@ -78,13 +78,12 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['uart']
-    probes = []
-    optional_probes = [
+    optional_channels = (
         # Allow specifying only one of the signals, e.g. if only one data
         # direction exists (or is relevant).
         {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
         {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
-    ]
+    )
     options = (
         {'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200},
         {'id': 'num_data_bits', 'desc': 'Data bits', 'default': 8,
@@ -101,22 +100,22 @@ class Decoder(srd.Decoder):
             'values': ('ascii', 'dec', 'hex', 'oct', 'bin')},
         # TODO: Options to invert the signal(s).
     )
-    annotations = [
-        ['rx-data', 'RX data'],
-        ['tx-data', 'TX data'],
-        ['rx-start', 'RX start bits'],
-        ['tx-start', 'TX start bits'],
-        ['rx-parity-ok', 'RX parity OK bits'],
-        ['tx-parity-ok', 'TX parity OK bits'],
-        ['rx-parity-err', 'RX parity error bits'],
-        ['tx-parity-err', 'TX parity error bits'],
-        ['rx-stop', 'RX stop bits'],
-        ['tx-stop', 'TX stop bits'],
-        ['rx-warnings', 'RX warnings'],
-        ['tx-warnings', 'TX warnings'],
-        ['rx-data-bits', 'RX data bits'],
-        ['tx-data-bits', 'TX data bits'],
-    ]
+    annotations = (
+        ('rx-data', 'RX data'),
+        ('tx-data', 'TX data'),
+        ('rx-start', 'RX start bits'),
+        ('tx-start', 'TX start bits'),
+        ('rx-parity-ok', 'RX parity OK bits'),
+        ('tx-parity-ok', 'TX parity OK bits'),
+        ('rx-parity-err', 'RX parity error bits'),
+        ('tx-parity-err', 'TX parity error bits'),
+        ('rx-stop', 'RX stop bits'),
+        ('tx-stop', 'TX stop bits'),
+        ('rx-warnings', 'RX warnings'),
+        ('tx-warnings', 'TX warnings'),
+        ('rx-data-bits', 'RX data bits'),
+        ('tx-data-bits', 'TX data bits'),
+    )
     annotation_rows = (
         ('rx-data', 'RX', (0, 2, 4, 6, 8)),
         ('rx-data-bits', 'RX bits', (12,)),