import sigrokdecode as srd
+'''
+Protocol output format:
+
+UART packet:
+[<packet-type>, <rxtx>, <packet-data>]
+
+This is the list of <packet-type>s and their respective <packet-data>:
+ - 'STARTBIT': The data is the (integer) value of the start bit (0/1).
+ - 'DATA': The data is the (integer) value of the UART data. Valid values
+ range from 0 to 512 (as the data can be up to 9 bits in size).
+ - 'PARITYBIT': The data is the (integer) value of the parity bit (0/1).
+ - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1).
+ - 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1).
+ - 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1).
+ - 'PARITY ERROR': The data is a tuple with two entries. The first one is
+ the expected parity value, the second is the actual parity value.
+ - TODO: Frame error?
+
+The <rxtx> field is 0 for RX packets, 1 for TX packets.
+'''
+
# Used for differentiating between the two data directions.
RX = 0
TX = 1
-# Annotation feed formats
-ANN_ASCII = 0
-ANN_DEC = 1
-ANN_HEX = 2
-ANN_OCT = 3
-ANN_BITS = 4
-
# Given a parity type to check (odd, even, zero, one), the value of the
# parity bit, the value of the data, and the length of the data (5-9 bits,
# usually 8 bits) return True if the parity is correct, False otherwise.
'parity_check': ['Check parity?', 'yes'], # TODO: Bool supported?
'num_stop_bits': ['Stop bit(s)', '1'], # String! 0, 0.5, 1, 1.5.
'bit_order': ['Bit order', 'lsb-first'],
+ 'format': ['Data format', 'ascii'], # ascii/dec/hex/oct/bin
# TODO: Options to invert the signal(s).
}
annotations = [
- ['ASCII', 'Data bytes as ASCII characters'],
- ['Decimal', 'Databytes as decimal, integer values'],
- ['Hex', 'Data bytes in hex format'],
- ['Octal', 'Data bytes as octal numbers'],
- ['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
+ ['RX data', 'UART RX data'],
+ ['TX data', 'UART TX data'],
+ ['Start bits', 'UART start bits'],
+ ['Parity bits', 'UART parity bits'],
+ ['Stop bits', 'UART stop bits'],
+ ['Warnings', 'Warnings'],
]
def putx(self, rxtx, data):
self.put(s - halfbit, s + halfbit, self.out_proto, data)
def __init__(self, **kwargs):
+ self.samplerate = None
self.samplenum = 0
self.frame_start = [-1, -1]
self.startbit = [-1, -1]
self.stopbit1 = [-1, -1]
self.startsample = [-1, -1]
self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
- self.oldbit = [None, None]
- self.oldpins = None
+ self.oldbit = [1, 1]
+ self.oldpins = [1, 1]
- def start(self, metadata):
- self.samplerate = metadata['samplerate']
- self.out_proto = self.add(srd.OUTPUT_PROTO, 'uart')
- self.out_ann = self.add(srd.OUTPUT_ANN, 'uart')
+ def start(self):
+ self.out_proto = self.register(srd.OUTPUT_PYTHON)
+ self.out_ann = self.register(srd.OUTPUT_ANN)
- # The width of one UART bit in number of samples.
- self.bit_width = \
- float(self.samplerate) / float(self.options['baudrate'])
+ def metadata(self, key, value):
+ if key == srd.SRD_CONF_SAMPLERATE:
+ self.samplerate = value;
+ # The width of one UART bit in number of samples.
+ self.bit_width = float(self.samplerate) / float(self.options['baudrate'])
def report(self):
pass
self.state[rxtx] = 'GET DATA BITS'
self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
- self.putg([ANN_ASCII, ['Start bit', 'Start', 'S']])
+ self.putg([2, ['Start bit', 'Start', 'S']])
def get_data_bits(self, rxtx, signal):
# Skip samples until we're in the middle of the desired data bit.
self.putp(['DATA', rxtx, self.databyte[rxtx]])
- s = 'RX: ' if (rxtx == RX) else 'TX: '
- self.putx(rxtx, [ANN_ASCII, [s + chr(self.databyte[rxtx])]])
- self.putx(rxtx, [ANN_DEC, [s + str(self.databyte[rxtx])]])
- self.putx(rxtx, [ANN_HEX, [s + hex(self.databyte[rxtx]),
- s + hex(self.databyte[rxtx])[2:]]])
- self.putx(rxtx, [ANN_OCT, [s + oct(self.databyte[rxtx]),
- s + oct(self.databyte[rxtx])[2:]]])
- self.putx(rxtx, [ANN_BITS, [s + bin(self.databyte[rxtx]),
- s + bin(self.databyte[rxtx])[2:]]])
+ b, f = self.databyte[rxtx], self.options['format']
+ if f == 'ascii':
+ self.putx(rxtx, [rxtx, [chr(b)]])
+ elif f == 'dec':
+ self.putx(rxtx, [rxtx, [str(b)]])
+ elif f == 'hex':
+ self.putx(rxtx, [rxtx, [hex(b)[2:].zfill(2).upper()]])
+ elif f == 'oct':
+ self.putx(rxtx, [rxtx, [oct(b)[2:].zfill(3)]])
+ elif f == 'bin':
+ self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]])
+ else:
+ raise Exception('Invalid data format option: %s' % f)
def get_parity_bit(self, rxtx, signal):
# If no parity is used/configured, skip to the next state immediately.
if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
self.databyte[rxtx], self.options['num_data_bits']):
self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
- self.putg([ANN_ASCII, ['Parity bit', 'Parity', 'P']])
+ self.putg([3, ['Parity bit', 'Parity', 'P']])
else:
# TODO: Return expected/actual parity values.
self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
- self.putg([ANN_ASCII, ['Parity error', 'Parity err', 'PE']])
+ self.putg([5, ['Parity error', 'Parity err', 'PE']])
# TODO: Currently only supports 1 stop bit.
def get_stop_bits(self, rxtx, signal):
# Stop bits must be 1. If not, we report an error.
if self.stopbit1[rxtx] != 1:
self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
+ self.putg([5, ['Frame error', 'Frame err', 'FE']])
# TODO: Abort? Ignore the frame? Other?
self.state[rxtx] = 'WAIT FOR START BIT'
self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([ANN_ASCII, ['Stop bit', 'Stop', 'P']])
+ self.putg([4, ['Stop bit', 'Stop', 'T']])
def decode(self, ss, es, data):
+ if self.samplerate is None:
+ raise Exception("Cannot decode without samplerate.")
# TODO: Either RX or TX could be omitted (optional probe).
for (self.samplenum, pins) in data:
# continue
self.oldpins, (rx, tx) = pins, pins
- # First sample: Save RX/TX value.
- if self.oldbit[RX] == None:
- self.oldbit[RX] = rx
- continue
- if self.oldbit[TX] == None:
- self.oldbit[TX] = tx
- continue
-
# State machine.
for rxtx in (RX, TX):
signal = rx if (rxtx == RX) else tx
projects / libsigrokdecode.git / blobdiff