# parity bit, the value of the data, and the length of the data (5-9 bits,
# usually 8 bits) return True if the parity is correct, False otherwise.
# 'none' is _not_ allowed as value for 'parity_type'.
-def parity_ok(parity_type, parity_bit, data, num_data_bits):
+def parity_ok(parity_type, parity_bit, data, data_bits):
if parity_type == 'ignore':
return True
class ChannelError(Exception):
pass
+class Ann:
+ RX_DATA, TX_DATA, RX_START, TX_START, RX_PARITY_OK, TX_PARITY_OK, \
+ RX_PARITY_ERR, TX_PARITY_ERR, RX_STOP, TX_STOP, RX_WARN, TX_WARN, \
+ RX_DATA_BIT, TX_DATA_BIT, RX_BREAK, TX_BREAK, RX_PACKET, TX_PACKET = \
+ range(18)
+
class Decoder(srd.Decoder):
api_version = 3
id = 'uart'
)
options = (
{'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200},
- {'id': 'num_data_bits', 'desc': 'Data bits', 'default': 8,
+ {'id': 'data_bits', 'desc': 'Data bits', 'default': 8,
'values': (5, 6, 7, 8, 9)},
- {'id': 'parity_type', 'desc': 'Parity type', 'default': 'none',
+ {'id': 'parity', 'desc': 'Parity', 'default': 'none',
'values': ('none', 'odd', 'even', 'zero', 'one', 'ignore')},
- {'id': 'num_stop_bits', 'desc': 'Stop bits', 'default': 1.0,
+ {'id': 'stop_bits', 'desc': 'Stop bits', 'default': 1.0,
'values': (0.0, 0.5, 1.0, 1.5)},
{'id': 'bit_order', 'desc': 'Bit order', 'default': 'lsb-first',
'values': ('lsb-first', 'msb-first')},
{'id': 'format', 'desc': 'Data format', 'default': 'hex',
'values': ('ascii', 'dec', 'hex', 'oct', 'bin')},
- {'id': 'invert_rx', 'desc': 'Invert RX?', 'default': 'no',
+ {'id': 'invert_rx', 'desc': 'Invert RX', 'default': 'no',
'values': ('yes', 'no')},
- {'id': 'invert_tx', 'desc': 'Invert TX?', 'default': 'no',
+ {'id': 'invert_tx', 'desc': 'Invert TX', 'default': 'no',
'values': ('yes', 'no')},
- {'id': 'rx_packet_delimiter', 'desc': 'RX packet delimiter (decimal)',
+ {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 50},
+ {'id': 'rx_packet_delim', 'desc': 'RX packet delimiter (decimal)',
'default': -1},
- {'id': 'tx_packet_delimiter', 'desc': 'TX packet delimiter (decimal)',
+ {'id': 'tx_packet_delim', 'desc': 'TX packet delimiter (decimal)',
'default': -1},
{'id': 'rx_packet_len', 'desc': 'RX packet length', 'default': -1},
{'id': 'tx_packet_len', 'desc': 'TX packet length', 'default': -1},
('tx-packet', 'TX packet'),
)
annotation_rows = (
- ('rx-data-bits', 'RX bits', (12,)),
- ('rx-data', 'RX', (0, 2, 4, 6, 8)),
- ('rx-warnings', 'RX warnings', (10,)),
- ('rx-break', 'RX break', (14,)),
- ('rx-packets', 'RX packets', (16,)),
- ('tx-data-bits', 'TX bits', (13,)),
- ('tx-data', 'TX', (1, 3, 5, 7, 9)),
- ('tx-warnings', 'TX warnings', (11,)),
- ('tx-break', 'TX break', (15,)),
- ('tx-packets', 'TX packets', (17,)),
+ ('rx-data-bits', 'RX bits', (Ann.RX_DATA_BIT,)),
+ ('rx-data', 'RX', (Ann.RX_DATA, Ann.RX_START, Ann.RX_PARITY_OK, Ann.RX_PARITY_ERR, Ann.RX_STOP)),
+ ('rx-warnings', 'RX warnings', (Ann.RX_WARN,)),
+ ('rx-break', 'RX break', (Ann.RX_BREAK,)),
+ ('rx-packets', 'RX packets', (Ann.RX_PACKET,)),
+ ('tx-data-bits', 'TX bits', (Ann.TX_DATA_BIT,)),
+ ('tx-data', 'TX', (Ann.TX_DATA, Ann.TX_START, Ann.TX_PARITY_OK, Ann.TX_PARITY_ERR, Ann.TX_STOP)),
+ ('tx-warnings', 'TX warnings', (Ann.TX_WARN,)),
+ ('tx-break', 'TX break', (Ann.TX_BREAK,)),
+ ('tx-packets', 'TX packets', (Ann.TX_PACKET,)),
)
binary = (
('rx', 'RX dump'),
def reset(self):
self.samplerate = None
- self.samplenum = 0
self.frame_start = [-1, -1]
self.frame_valid = [None, None]
self.startbit = [-1, -1]
self.out_python = self.register(srd.OUTPUT_PYTHON)
self.out_binary = self.register(srd.OUTPUT_BINARY)
self.out_ann = self.register(srd.OUTPUT_ANN)
- self.bw = (self.options['num_data_bits'] + 7) // 8
+ self.bw = (self.options['data_bits'] + 7) // 8
def metadata(self, key, value):
if key == srd.SRD_CONF_SAMPLERATE:
def get_sample_point(self, rxtx, bitnum):
# Determine absolute sample number of a bit slot's sample point.
- # bitpos is the samplenumber which is in the middle of the
- # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit
- # (if used) or the first stop bit, and so on).
- # The samples within bit are 0, 1, ..., (bit_width - 1), therefore
- # index of the middle sample within bit window is (bit_width - 1) / 2.
- bitpos = self.frame_start[rxtx] + (self.bit_width - 1) / 2.0
+ # Counts for UART bits start from 0 (0 = start bit, 1..x = data,
+ # x+1 = parity bit (if used) or the first stop bit, and so on).
+ # Accept a position in the range of 1-99% of the full bit width.
+ # Assume 50% for invalid input specs for backwards compatibility.
+ perc = self.options['sample_point'] or 50
+ if not perc or perc not in range(1, 100):
+ perc = 50
+ perc /= 100.0
+ bitpos = (self.bit_width - 1) * perc
+ bitpos += self.frame_start[rxtx]
bitpos += bitnum * self.bit_width
return bitpos
# for the next start bit (assuming this one was spurious).
if self.startbit[rxtx] != 0:
self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]])
- self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']])
+ self.putg([Ann.RX_WARN + rxtx, ['Frame error', 'Frame err', 'FE']])
self.frame_valid[rxtx] = False
es = self.samplenum + ceil(self.bit_width / 2.0)
self.putpse(self.frame_start[rxtx], es, ['FRAME', rxtx,
self.startsample[rxtx] = -1
self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
- self.putg([rxtx + 2, ['Start bit', 'Start', 'S']])
+ self.putg([Ann.RX_START + rxtx, ['Start bit', 'Start', 'S']])
self.state[rxtx] = 'GET DATA BITS'
def handle_packet(self, rxtx):
d = 'rx' if (rxtx == RX) else 'tx'
- delim = self.options[d + '_packet_delimiter']
+ delim = self.options[d + '_packet_delim']
plen = self.options[d + '_packet_len']
if delim == -1 and plen == -1:
return
s += ' '
if self.options['format'] != 'ascii' and s[-1] == ' ':
s = s[:-1] # Drop trailing space.
- self.putx_packet(rxtx, [16 + rxtx, [s]])
+ self.putx_packet(rxtx, [Ann.RX_PACKET + rxtx, [s]])
self.packet_cache[rxtx] = []
def get_data_bits(self, rxtx, signal):
if self.startsample[rxtx] == -1:
self.startsample[rxtx] = self.samplenum
- self.putg([rxtx + 12, ['%d' % signal]])
+ self.putg([Ann.RX_DATA_BIT + rxtx, ['%d' % signal]])
# Store individual data bits and their start/end samplenumbers.
s, halfbit = self.samplenum, int(self.bit_width / 2)
# Return here, unless we already received all data bits.
self.cur_data_bit[rxtx] += 1
- if self.cur_data_bit[rxtx] < self.options['num_data_bits']:
+ if self.cur_data_bit[rxtx] < self.options['data_bits']:
return
# Convert accumulated data bits to a data value.
# Advance to either reception of the parity bit, or reception of
# the STOP bits if parity is not applicable.
self.state[rxtx] = 'GET PARITY BIT'
- if self.options['parity_type'] == 'none':
+ if self.options['parity'] == 'none':
self.state[rxtx] = 'GET STOP BITS'
def format_value(self, v):
# Reflects the user selected kind of representation, as well as
# the number of data bits in the UART frames.
- fmt, bits = self.options['format'], self.options['num_data_bits']
+ fmt, bits = self.options['format'], self.options['data_bits']
# Assume "is printable" for values from 32 to including 126,
# below 32 is "control" and thus not printable, above 127 is
def get_parity_bit(self, rxtx, signal):
self.paritybit[rxtx] = signal
- if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
- self.datavalue[rxtx], self.options['num_data_bits']):
+ if parity_ok(self.options['parity'], self.paritybit[rxtx],
+ self.datavalue[rxtx], self.options['data_bits']):
self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
- self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']])
+ self.putg([Ann.RX_PARITY_OK + rxtx, ['Parity bit', 'Parity', 'P']])
else:
# TODO: Return expected/actual parity values.
self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
- self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']])
+ self.putg([Ann.RX_PARITY_ERR + rxtx, ['Parity error', 'Parity err', 'PE']])
self.frame_valid[rxtx] = False
self.state[rxtx] = 'GET STOP BITS'
# Stop bits must be 1. If not, we report an error.
if self.stopbit1[rxtx] != 1:
self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']])
+ self.putg([Ann.RX_WARN + rxtx, ['Frame error', 'Frame err', 'FE']])
self.frame_valid[rxtx] = False
self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']])
+ self.putg([Ann.RX_PARITY_OK + rxtx, ['Stop bit', 'Stop', 'T']])
# Pass the complete UART frame to upper layers.
es = self.samplenum + ceil(self.bit_width / 2.0)
self.putpse(self.frame_start[rxtx], self.samplenum,
['BREAK', rxtx, 0])
self.putgse(self.frame_start[rxtx], self.samplenum,
- [rxtx + 14, ['Break condition', 'Break', 'Brk', 'B']])
+ [Ann.RX_BREAK + rxtx, ['Break condition', 'Break', 'Brk', 'B']])
self.state[rxtx] = 'WAIT FOR START BIT'
def get_wait_cond(self, rxtx, inv):
elif state == 'GET DATA BITS':
bitnum = 1 + self.cur_data_bit[rxtx]
elif state == 'GET PARITY BIT':
- bitnum = 1 + self.options['num_data_bits']
+ bitnum = 1 + self.options['data_bits']
elif state == 'GET STOP BITS':
- bitnum = 1 + self.options['num_data_bits']
- bitnum += 0 if self.options['parity_type'] == 'none' else 1
+ bitnum = 1 + self.options['data_bits']
+ bitnum += 0 if self.options['parity'] == 'none' else 1
want_num = ceil(self.get_sample_point(rxtx, bitnum))
return {'skip': want_num - self.samplenum}
# Determine the number of samples for a complete frame's time span.
# A period of low signal (at least) that long is a break condition.
frame_samples = 1 # START
- frame_samples += self.options['num_data_bits']
- frame_samples += 0 if self.options['parity_type'] == 'none' else 1
- frame_samples += self.options['num_stop_bits']
+ frame_samples += self.options['data_bits']
+ frame_samples += 0 if self.options['parity'] == 'none' else 1
+ frame_samples += self.options['stop_bits']
frame_samples *= self.bit_width
self.frame_len_sample_count = ceil(frame_samples)
self.break_min_sample_count = self.frame_len_sample_count
projects / libsigrokdecode.git / blobdiff