##
import sigrokdecode as srd
+from math import floor, ceil
'''
OUTPUT_PYTHON format:
This is the list of <ptype>s and their respective <pdata> values:
- 'STARTBIT': The data is the (integer) value of the start bit (0/1).
- - ('DATA', 'DATABITS'): DATA is the (integer) value of the UART data. Valid
- values range from 0 to 512 (as the data can be up to 9 bits in size).
- 'DATABITS' is the list of individual data bits and their ss/es numbers.
+ - 'DATA': This is always a tuple containing two items:
+ - 1st item: the (integer) value of the UART data. Valid values
+ range from 0 to 512 (as the data can be up to 9 bits in size).
+ - 2nd item: the list of individual data bits and their ss/es numbers.
- 'PARITYBIT': The data is the (integer) value of the parity bit (0/1).
- 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1).
- 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1).
('tx', 'TX dump'),
('rxtx', 'RX/TX dump'),
)
+ idle_state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
def putx(self, rxtx, data):
- s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
- self.put(s - halfbit, self.samplenum + halfbit, self.out_ann, data)
+ s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
+ self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data)
def putpx(self, rxtx, data):
- s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
- self.put(s - halfbit, self.samplenum + halfbit, self.out_python, data)
+ s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
+ self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_python, data)
def putg(self, data):
- s, halfbit = self.samplenum, int(self.bit_width / 2)
- self.put(s - halfbit, s + halfbit, self.out_ann, data)
+ s, halfbit = self.samplenum, self.bit_width / 2.0
+ self.put(s - floor(halfbit), s + ceil(halfbit), self.out_ann, data)
def putp(self, data):
- s, halfbit = self.samplenum, int(self.bit_width / 2)
- self.put(s - halfbit, s + halfbit, self.out_python, data)
+ s, halfbit = self.samplenum, self.bit_width / 2.0
+ self.put(s - floor(halfbit), s + ceil(halfbit), self.out_python, data)
def putbin(self, rxtx, data):
- s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
- self.put(s - halfbit, self.samplenum + halfbit, self.out_bin, data)
+ s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
+ self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_binary, data)
- def __init__(self, **kwargs):
+ def __init__(self):
self.samplerate = None
self.samplenum = 0
self.frame_start = [-1, -1]
self.startsample = [-1, -1]
self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
self.oldbit = [1, 1]
- self.oldpins = [1, 1]
+ self.oldpins = [-1, -1]
self.databits = [[], []]
def start(self):
self.out_python = self.register(srd.OUTPUT_PYTHON)
- self.out_bin = self.register(srd.OUTPUT_BINARY)
+ self.out_binary = self.register(srd.OUTPUT_BINARY)
self.out_ann = self.register(srd.OUTPUT_ANN)
def metadata(self, key, value):
# bitpos is the samplenumber which is in the middle of the
# specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit
# (if used) or the first stop bit, and so on).
- bitpos = self.frame_start[rxtx] + (self.bit_width / 2.0)
+ # The samples within bit are 0, 1, ..., (bit_width - 1), therefore
+ # index of the middle sample within bit window is (bit_width - 1) / 2.
+ bitpos = self.frame_start[rxtx] + (self.bit_width - 1) / 2.0
bitpos += bitnum * self.bit_width
if self.samplenum >= bitpos:
return True
# The startbit must be 0. If not, we report an error.
if self.startbit[rxtx] != 0:
self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]])
+ self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']])
# TODO: Abort? Ignore rest of the frame?
self.cur_data_bit[rxtx] = 0
elif f == 'bin':
self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]])
- self.putbin(rxtx, (rxtx, bytes([b])))
- self.putbin(rxtx, (2, bytes([b])))
+ self.putbin(rxtx, [rxtx, bytes([b])])
+ self.putbin(rxtx, [2, bytes([b])])
- self.databits = [[], []]
+ self.databits[rxtx] = []
def get_parity_bit(self, rxtx, signal):
# If no parity is used/configured, skip to the next state immediately.
# Stop bits must be 1. If not, we report an error.
if self.stopbit1[rxtx] != 1:
self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([rxtx + 8, ['Frame error', 'Frame err', 'FE']])
+ self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']])
# TODO: Abort? Ignore the frame? Other?
self.state[rxtx] = 'WAIT FOR START BIT'
raise SamplerateError('Cannot decode without samplerate.')
for (self.samplenum, pins) in data:
- # Note: Ignoring identical samples here for performance reasons
- # is not possible for this PD, at least not in the current state.
- # if self.oldpins == pins:
- # continue
+ # We want to skip identical samples for performance reasons but,
+ # for now, we can only do that when we are in the idle state
+ # (meaning both channels are waiting for the start bit).
+ if self.state == self.idle_state and self.oldpins == pins:
+ continue
+
self.oldpins, (rx, tx) = pins, pins
if self.options['invert_rx'] == 'yes':
projects / libsigrokdecode.git / blobdiff