adxl345: Fix scale factor in handle_reg_0x22().

[libsigrokdecode.git] / decoders / uart / pd.py

diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index 67f4c7e702760e3d76f92695c58de08bf3719564..0c501b0dc46d63c5321c60472b750def28525c9d 100644 (file)
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -88,6 +88,9 @@ class Ann:
     RX_DATA_BIT, TX_DATA_BIT, RX_BREAK, TX_BREAK, RX_PACKET, TX_PACKET = \
     range(18)
 
+class Bin:
+    RX, TX, RXTX = range(3)
+
 class Decoder(srd.Decoder):
     api_version = 3
     id = 'uart'
@@ -131,18 +134,18 @@ class Decoder(srd.Decoder):
     annotations = (
         ('rx-data', 'RX data'),
         ('tx-data', 'TX data'),
-        ('rx-start', 'RX start bits'),
-        ('tx-start', 'TX start bits'),
-        ('rx-parity-ok', 'RX parity OK bits'),
-        ('tx-parity-ok', 'TX parity OK bits'),
-        ('rx-parity-err', 'RX parity error bits'),
-        ('tx-parity-err', 'TX parity error bits'),
-        ('rx-stop', 'RX stop bits'),
-        ('tx-stop', 'TX stop bits'),
-        ('rx-warnings', 'RX warnings'),
-        ('tx-warnings', 'TX warnings'),
-        ('rx-data-bits', 'RX data bits'),
-        ('tx-data-bits', 'TX data bits'),
+        ('rx-start', 'RX start bit'),
+        ('tx-start', 'TX start bit'),
+        ('rx-parity-ok', 'RX parity OK bit'),
+        ('tx-parity-ok', 'TX parity OK bit'),
+        ('rx-parity-err', 'RX parity error bit'),
+        ('tx-parity-err', 'TX parity error bit'),
+        ('rx-stop', 'RX stop bit'),
+        ('tx-stop', 'TX stop bit'),
+        ('rx-warning', 'RX warning'),
+        ('tx-warning', 'TX warning'),
+        ('rx-data-bit', 'RX data bit'),
+        ('tx-data-bit', 'TX data bit'),
         ('rx-break', 'RX break'),
         ('tx-break', 'TX break'),
         ('rx-packet', 'RX packet'),
@@ -150,14 +153,14 @@ class Decoder(srd.Decoder):
     )
     annotation_rows = (
         ('rx-data-bits', 'RX bits', (Ann.RX_DATA_BIT,)),
-        ('rx-data', 'RX', (Ann.RX_DATA, Ann.RX_START, Ann.RX_PARITY_OK, Ann.RX_PARITY_ERR, Ann.RX_STOP)),
+        ('rx-data-vals', 'RX data', (Ann.RX_DATA, Ann.RX_START, Ann.RX_PARITY_OK, Ann.RX_PARITY_ERR, Ann.RX_STOP)),
         ('rx-warnings', 'RX warnings', (Ann.RX_WARN,)),
-        ('rx-break', 'RX break', (Ann.RX_BREAK,)),
+        ('rx-breaks', 'RX breaks', (Ann.RX_BREAK,)),
         ('rx-packets', 'RX packets', (Ann.RX_PACKET,)),
         ('tx-data-bits', 'TX bits', (Ann.TX_DATA_BIT,)),
-        ('tx-data', 'TX', (Ann.TX_DATA, Ann.TX_START, Ann.TX_PARITY_OK, Ann.TX_PARITY_ERR, Ann.TX_STOP)),
+        ('tx-data-vals', 'TX data', (Ann.TX_DATA, Ann.TX_START, Ann.TX_PARITY_OK, Ann.TX_PARITY_ERR, Ann.TX_STOP)),
         ('tx-warnings', 'TX warnings', (Ann.TX_WARN,)),
-        ('tx-break', 'TX break', (Ann.TX_BREAK,)),
+        ('tx-breaks', 'TX breaks', (Ann.TX_BREAK,)),
         ('tx-packets', 'TX packets', (Ann.TX_PACKET,)),
     )
     binary = (
@@ -329,8 +332,8 @@ class Decoder(srd.Decoder):
             self.putx(rxtx, [rxtx, [formatted]])
 
         bdata = b.to_bytes(self.bw, byteorder='big')
-        self.putbin(rxtx, [rxtx, bdata])
-        self.putbin(rxtx, [2, bdata])
+        self.putbin(rxtx, [Bin.RX + rxtx, bdata])
+        self.putbin(rxtx, [Bin.RXTX, bdata])
 
         self.handle_packet(rxtx)
 
@@ -410,7 +413,7 @@ class Decoder(srd.Decoder):
             self.frame_valid[rxtx] = False
 
         self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
-        self.putg([Ann.RX_PARITY_OK + rxtx, ['Stop bit', 'Stop', 'T']])
+        self.putg([Ann.RX_STOP + rxtx, ['Stop bit', 'Stop', 'T']])
 
         # Pass the complete UART frame to upper layers.
         es = self.samplenum + ceil(self.bit_width / 2.0)